Can't run FPGA through Host

[soljiang]

My program ran normally this afternoon but after I saved the file again (seems without any change), I can no longer see wave in wave chart any more when launching the Host vi.  Only when I keep the FPGA vi running can the wave be displayed on the chart.  I don't understand what happened.  I used Run as the invode method but seems I can't run FPGA through Host vi any more.  Any help will be very much appreciated.  I also attached both FPGA and Host vi, which is hardly changed from the examples. 

[StephenB · Accepted solution]

You don't need the run invoke method as your open FPGA VI reference is currently configured to automatically run the VI. I'd recommend either removing the invoke method or right clicking your open FPGA VI reference and changing its options so that it doesn't auto run.

The way you are transferring your data between your FPGA and host VI could be the problem. Currently on your FPGA VI you have a waveform chart and a bundle function. Typically, you don't want any front panel graphics on an FPGA VI, as it acts as just the low level code doing your FPGA level tasks. You view your data when you pass it back to your host. Also, there is no reason to bundle a single piece of data into a cluster, you can just make a I16 indicator.

Additionally, I don't understand the timing of the system, perhaps I'm just confused here. Your default front panel value for loop rate configures the FPGA VI to grab a new AI sample every 100uS. Which means the FPGA is going to be asserting an interrupt 10,000 times a second. You have your host VI set up to wait for an interrupt before reading the indicator, but the host is configured to run every 10ms, or 100 times a second. Basically, you have your FPGA and your Host VI running at orders of magnitude different rates, but are trying to sync the reads with an interrupt.

You can run the FPGA and host VIs at different rates successfully by using a DMA FIFO, or a queue, between them. So that your FPGA VI is grabbing samples really fast and packing them into a queue one at a time for the host VI to grab a whole chunk of at a slower interval. There is a great document on how to do this here: http://zone.ni.com/devzone/cda/tut/p/id/4534

[soljiang]

Thank you soooo much, Stephen!!!  After following your advice, I solve my problem.  Also I tried FIFO method recommended by you and it also worked fine.  I truly appreciate your help!  😄

[eug]

Hi everyone,

I'm using cRIO 9012 and I've the same problem...I cannot run the FPGA VI from the host program...Attached there are the two VIs...What do I do wrong?

thanks

[Doug-B]

Hey eug,

I looked at your VIs and nothing really jumped out at me as being incorrect. If you could describe for me exactly what is going wrong for you that would be helpful. I know you said that it was the same as what was originally posted but that was back in 2009 and a lot has changed with LabVIEW since then and I want to make sure we are on the same page.

Thanks,

Doug B

[eug]

Hi Doug, Thanks a lot for your answer, I try to briefly explain my issue....I'm using labview 2011 and I've created a FPGA project with just the two VIs I attacched in my first message. If I manually start the FPGA vi and then the HOST vi everything is ok, but if I run just the host vi (where the FPGA open reference is set to automatically run also the FPGA VI) the FPGA vi does not start and consequently the behavior is not what I expect. I hope this clarifies my problem Thanks again Eug

[Doug-B]

Hey eug,

You have the Open FPGA Reference VI configured to "Open and Run" correct? If so, when the RT code gets to that point in its execution, the FPGA VI should start running. Make sure that the FPGA VI is compiled down to the FPGA backplane, if so, then something is going wrong. I just want to make sure everything is set up correctly on your end first.

Regards,

Doug B