Constraints/Output Buffer for FPGA Pins (e.g. PXI_LBLSTAR0)

[TilmanJurk]

Hi anybody,
is there a way to change the output options for the pins provided in the FPGA files?

For example: in the UCF file for the 8711R FPAG Board, there are constraints set for nearly any of the FPGA lines.

<snip>

NET "PXI_LBLSTAR0" IOSTANDARD = LVTTL;
NET "PXI_LBLSTAR0" DRIVE = 6;

NET "PXI_LBLSTAR0" SLOW;

<snip>

What, if i want to change the output driver to HIGH Speed?

Is there a way to do this in the LabVIEW project/VI

Thks in advance for your time.

/Tilman

[Vans]

Hi Tilman,

am I right that you try to modify the UCF file? Unfortunately, we won't support that change. It will be your responsibility to modify parameters.

Kind Regards,

Vanessa

[TilmanJurk]

Well, you are using very conservative settings in the provided ucf file.

Even PXI-SIgnals should be used at the highest possible speed.

BR

Tilman

[Vans]

Hi Tilman,

it would be helpful to get some more informations.

I think you use the 7811R board. Which IP block do you use? You say "provided ucf file". Where did you get it from? What is the name of your ucf file?

I will do my best to support you but do not expect to much.

Kind Regards,

Vanessa

[TilmanJurk]

Hi Vanessa,

yes, you´re right, i am using a 7811R board.

The UCF file is the one delivered with the FPGA distribution of LabVIEW.

It is located in C:\Program Files\National Instruments\LabVIEW 2013\Targets\NI\FPGA\RIO\R Series\PXI-7811R\VHDL and it is named "toplevel_gen.ucf".

I assume that it is used as a template in any FPGA design related to the 7811R Board.

Hope this helps.

Thanks again for your time.

BR

/Tilman

[Vans]

Hi Tilman,

I am sorry. I asked my colleagues but it is not supported to change this ucf files.

There are several risks involved: Using this workaround will change this setting for any and all VIs compiled from this computer. This will affect any Reconfigurable I/O targets that you compile the VI for. In other words, this could cause problems if you are targetting devices other than the 7811R. There is no indication on the VI that the drive strength has been changed. Therefore, you must keep track of these settings. When changing the Driver Type to a setting other than the default, you are increasing the likelihood of cross-talk between Digital lines. Chaging other options in the toplevel_gen.ucf could cause some undesirable affects.

I hope you will get along with the default settings.

Kind Regards,
Vanessa

[TilmanJurk]

Hi Vanessa,

thanks for your information.

I think that i can change change the settings in the ucf file if i track any changes and revert the ucf file to the default after each (special) build.

Even if you are using high pseed outputs, the drive options may be adopted to the needs.

Anyway, the safe way is to leave the provided file as is.

Thanks for your time.

BR

Tilman

[Michael_78]

Hi Tilman,

I have an interest in this thread.  I found the ucf files when i needed to check exact placing within the fpga fabric, i.e. which pins were mapped to the FPGA IO.  I thought about making changes but never needed to.  Like you, i considered tracking the UCF as part of the build process and being very careful between builds.  I would be interested to know if you ever changed the file? did you have any success? any problems?  I know it will never be NI supported, but it could be very useful, especially with SBRIO targets.

MIchael.

[TilmanJurk]

Hi Michael,

I did not change anything in the UCF file, nor used in in a specia way. I will check this - especially changing the drive strength options - in the (near) future.

Sorry about that.

BR

Tilman

[Michael_78]

thanks,

lets keep this thread going for future discussion.  I have a colleague who will be interested too.

Michael.