Correct DMA BufferSize

[bradh]

May application

• Using cRIO 9074 with three 9239 modules (4 channels in each module)
• Acquiring 12 total channels at 25kHz into an array, continuous acq
• Using DMA for transfer from target to host
• Reading the buffer on the host with a timed loop set to "Synch to Scan Engine" (Scan time on host is set to 10ms)

I am confused on the proper FPGA and host buffer size. 

Each host loop (10ms), I would be creating 12*25k*0.010= 3000 elements.

Do I set the FPGA side to exactly 3000 elements and the host size to 3-4 times this?  (Both sides though to a multiple of 12)

[David_L]

For the Host side, it depends on how fast you are reading from the FIFO and and how big your chunks are.  If you are reading just as fast as you are writing, then you can leave the buffer to be 1X.  But if you read slower, you need to compensate for this and increase the buffer size.  If you have Memory and FPGA space to spare, it can't hurt to have too big of a buffer...