DMA unstability problem at FPGA start

[Daniel_Chile]

Hi Basset,
Technical support has not contacted me until now. Is there any way I can send you the project directly?
Thank you,

Daniel R.
CLD
Chile

[Bassett_Hound]

Hi Daniel,

Has Technical support contacted you yet?  They should have by now if its been a day.  Did you get an Service Request number when you created your request?  In our communcation absence I've been looking into this a little further and wanted to see if you could try a couple other debugging steps.

First, are you using the Minimal Recommended Software Stack?  If not, lets install this to the controller and see if you get the behavior.

Second, If the first step shows improvement, lets re-install the Full Recommended Software Set, and then keep removing items until the issue disappears.  I would start with NI Serial and the Modbus I/O Server.

If you have the Service Request number I can followup and see why you haven't been contacted so I can do the debugging steps mentioned above.

Thanks,

Basset Hound

[akokot]

Hi Daniel and Basset,

I'm from the support in Brazil. Daniel, we received your request but there isn't any attached code. I sent you an e-mail, you can reply to this e-mail with the code.

Regards,
Alisson Kokot
AE BRAZIL

[Daniel_Chile]

Hi Basset and Alisson.
Fortunately, we already made a workaround to this problem. However, we are sending the code to see if this can be fixed.

We will also try what Basset Hound suggested to check if it is a drivers problem.

By the way, Basset, support reference is 7200141.

Thanks a lot.

Daniel R.
CLD
Chile

[Bassett_Hound]

Hi Daniel,

Thank you for the support reference and please do send in the code so we can root cause this issue.  Can you also explain how you worked around this issue?

Thanks,

Basset Hound

[akokot]

Hi Basset,

I received the code from Daniel. It's a huge code. You could contact in the Sametime or by e-mail. The code is documented in spanish, so if you need some help you can ask me.

Regards
Alisson Kokot
AE Brazil

[Daniel_Chile]

Yes, it's a big code and is not really documented.

These days, at the same time we are moving this code to CompactRIO, we are refactoring it.

Regarding the workaournd:

Normally our app starts, performs data acquisition for 20-30 minutes, pauses for a couple of seconds and then starts acquisition again (and so on).

We loaded, executed and aborted FPGA for every data acquisition cycle.

As the FIFOs problem presented when loading and starting the FPGA, now we load the FPGA once (persistently) at the program start, even before entering the state machine, and then it just goes to a "sleep" state when pausing. This way we avoid loading the FPGA every time acquisition starts.

It has worked well, but we would like to know why the previous version didn't work.

To run the app you must put the "config*.var" file in "ni-rt\startup" and run TOP_ADQ.vi. You can open the front panels of "subVIs nuevos\Carga_FPGA_Persistente.vi" and "subVIs nuevos\FPGAListo.vi" to check the progress of the load of FPGA.

Once acquisition started successfully (if so), hit "Detener por usuario" to return to pause and start acquisition again.

Please tell me if you can reproduce the issue.

Thank you

Daniel R.
CLD
Chile