DRAM - FIFO 'always' FULL

[CyGa]

Hi !

Currently working on data streaming with a 7952R board associated to a 6585 adapter, I'm trying to use the DRAM as a FIFO to store my data and then return data back to the host using a DMA.

The acquisition loops runs at 125MHz (derived clock from the 40MHz onbaord clock).

Whatever the structure i'm using I'm facing always the same problem : FIFO returns status FULL, but there should still be space free in the FIFO.

I attached some code I made, if someone can look at it and tell me what could be wrong...

The interesting  VIs are 'FPGA_ValidDRAM_xxxxxxxxx.vi '.

Thanks !

[Antonin_G. · Accepted solution]

Hello zyl7,

When you say "FIFO returns allways FULL, but there should still be space free in the FIFO" do you mean DRAM Full indicator is set as true ? or do you have an error occuring each time you running the application ?

Moreover, it may be possible for the FULL node to show a TRUE at high speeds (higher than 40MHz), because its memory abritration CLIP may need to some time before it perform any writes.

Did you check the behaviour at 40MHz or 100MHz ?

Regards,

[CyGa]

Indeed, it's not recommended to use the CLIP @ speed greater than 40MHz.

I had another issue with DRAM @100MHz using the NI interface : I'm seeing data shifting when storing and then requesting data from the DRAM. I'll post another message with the example for that issue.

Thanks.