12-06-2007 10:40 AM
12-06-2007 11:48 AM
I forgot to mention that the first I do in the FPGA vi is to reset the variable connected to the "System Reset" IO node to false.
Patrick
12-06-2007 12:08 PM
Sorry. Everything works fine. It was my error. I was closing the FPGA reference after settting my reboot variable to TRUE which is in a loop executed every 500 ms. The reference was close before the variable was read.