Dynamically change FPGA programs

[Steve_Brooks]

I have a program that needs to swap FPGA programs dynamically.  I have a subVI in the real-time that executes this function but sometimes (over 50%) receives an error -61141 which is explained as "FPGA is busy".  The error always occurs at the open reference.  I know that the current FPGA stops because I am monitoring the outputs.  Here is a link to a picture of the block diagram:

http://picasaweb.google.com/lh/photo/BxZp4jVinxA3lqyg4_OMzQ?feat=directlink

Any help is appreciated,

-Steve

[kikiduu]

Will it help if you just increase the delay between closing the refernce and opening a new one. May be you can vary it and find an optimum delay.

[Steve_Brooks]

That is a good suggestion, but we have tried to run this in execution highlight even with physically pausing for 5 - 10 seconds between the close and open.  This still doesn't seem to have any effect.

[Christian_L]

Steve,

Which version of LV and LV FPGA are you using? What FPGA target (R series card, cRIO chassis, etc.) are you using? What host processor (PXI controller, cRIO controller, etc.) are you using?

[Brinoceros]

Hi Steve,

I have a couple of thoughts.  First of all, are you dealing with multiple FPGA's or is this just with a single piece of hardware.  Iis the FPGA remote, or in the local system?  Also, are you dealing with any other FPGA references elsewhere in your code? Finally, is the error generated at the Open Reference, or elsewhere?

Try changing the Close Reference to just Close (not reset).  You can do this from the right-click menu on the Close Reference VI.

[Steve_Brooks]

To answer Christian's questions:

This is hosted on a cRIO 9074; LabVIEW ver 8.6; RT ver 8.6; FPGA ver 8.6; NI RIO ver 3.0

To answer Brian's questions:

This project is a single 9074 FPGA target through a network so it is listed as a remote system.  This is the only FPGA reference in the code and the error always comes from the Open Reference VI.  For the close reference VI, I have tried both Close and Close & Reset.  In both configurations the open reference returns the error.

-Steve

[JMota]

Hey Steve, from the block diagram you show I can't tell if you are closing the second FPGA reference you are opening? Can you verify that's the case? (sorry for asking the obvious, but sometimes obvious solutions take forever to find them ). Also, have you tried simplifying your code to see if you can reproduce it without going through VI boundaries? Are you calling VIs by reference?

[Steve_Brooks]

Obvious questions are never bad in my book.

Yes, if the user switches back to the record the second ref is closed.  There is also a close in the exit case.  This VI is not dynamically called, it is a regular subVI.  At one point early in development this was not a subVI, I will try pulling that up to the top level in the RT.

-Steve

[The Specialist]

Hi Steve,

I guess I'll jump in.  First, why are you switching FPGA files?  Have you reached the maximum size of your FPGA, or is this part of some grander scheme. I ask because the easiest solution would be to just combine the two together.

[Steve_Brooks]

Good question, but yes it is part of a grander scheme.  First, we are using this as a baseline architecture going ahead.  Second, I am using multiple FPGA files due to DMA limitations.  Both of my FPGA files use two DMA channels each, the maximum per FPGA is three.

-Steve