Re : Engine cylinder pressure vs CAD

[Simon_etu]

Hello,

I'm a new user on labview and I have some questions about a project which I am working on.

I need to take a pressure signal in the cylinder and link it with the crank shaft angle (CAD for crank angle degree)

I have a cRIO 9014, an NI 9215 (4 analog input, I just using one for the pressure signal) and an NI 9401 used to wire the encoder.

My encoder is a ROD 420 (3600 ppr).

So my first problem is for the FPGA vi, I need to take the signal pressure each time there is a new count on my encoder (so each 0.1 deg).

1. How can I synchronize the two measurement ? because if I well understand, I can't use FIFO here because I cannot pass the encoder position with the FIFO ?

2. I using shared variable to transfer data from the RT vi to the Host vi on the computer. May I lose some data with this option ?

3. And finnaly I want to start reading value on my Host vi from the shared variable as soon as a CAD 0 appear. How can I implement that ?

You can find in attachment my project

Best regards,

Simon

[Aurel.Co]

Hi Simon_etu,

I'm sorry,but what does CAD means?

I don't see the relation beetween synchronisation and fifo in your case.

To transfert variable beetween your FPGA and your RT Host, you can use DMA FIFO.

To transfer variable beetwen your RT Host and yourt HOST, you can use RT FIFO

You won't loose data using this kind of FIFO.

Best regards

[Simon_etu]

Thanks for the answer,

CAD (for crank angle degree) represent the angle position of the crankshaft. commonly we use as reference (0 deg CAD) the position of the crankshaft when the piston is in the higher position in the cylinder in other words, when the volume available in the cylinder is in his lower level. So CAD goes from -360deg to 360deg (or 0 to 720, depend on the 0 reference) because for 1 motor cycle the crankshaft performs 2 rotations.

I talked about synchronization because I want to take the pressure signal only if a new count appears on my decoder.

I build something with a case structure but I'd like to have some opinion or advice because I'm not sure of my implementation.

So I used DMA FIFO to transfer the data from the FPGA to the RT.

Then I read data in the RT Host but I'm not sure of what timing use for the timed loop where the fifo is reading.

The engine speed is around 1500 rpm ; 1 cycle corresponding to two rotation ; I must have 3600 value per rotation (because the encoder have 3600ppr) so 7200 value per cycle.

Then I thought about using a shared variable with fifo enable to transfer array of data (7200 value) to my Host.

Is it efficient ? Or do I have to use something else to perform this transfer.

See in attachment my FPGA and RT vi

Each advices or comments are welcome,

Best regards

Simon

[Simon_etu]

I just tried to compile my FPGA vi.

Indeed it's seems that the way I used to implement my vi to take a pressure signal only when a new count appears on my encoder doesn't work

about the analog input :

''The selected object takes one or more clock cycles to execute.

Remove the object from the single-cycle Timed Loop or replace the single-cycle Timed Loop with a While Loop.''

so how can I implement that ?