Hi,
I am trying to simulate a 1024x16 FIFO using coregen using VHDL. I have declared the entity myself and copied the remaining code from .vho file of the coregen (as explained in various online tutorials). Although my code is being sythesized correctly, in simulation, I am getting a warning like:-
WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst
and the output is coming 'uninitialized' (red lines)
Following is the code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity fifo2_my is
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end fifo2_my;
architecture Behavioral of fifo2_my is
component fifo2
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
data_count: OUT std_logic_VECTOR(9 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
valid: OUT std_logic;
underflow: OUT std_logic;
wr_ack: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo2: component is true;
UUT : fifo2
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
data_count => data_count,
dout => dout,
empty => empty,
full => full,
overflow => overflow,
valid => valid,
underflow => underflow,
wr_ack => wr_ack);
end Behavioral;
Plz help!!
