FPGA SCTL: Not Gate change timing of the Digital output signal

[Tphan]

Hello All,

 I am struggle with the timing of the output signal while trying to generate differential signal out put pair. I suppose was simple as add a not gate to the first signal then I can can have the 2nd signal revert.  Well, it did revert but the timing is off.  they are not out put at the same time.  One is delay a haft cycle time compare to the other.  This is execute in a SCTL.  Any idea?

Thanks

Tphan

[nanocyte]

What hardware are you using (model?)

Some DIO to DIO skew is to be expected. It might be random and vary from bit file to bit file. See https://www.ni.com/en/support/documentation/supplemental/11/rio-mezzanine-card-digital-i-o-capabilit...

 Also, it might be useful to post a code snippet or maybe a VI and project just so to be totally sure there's no issues there.

[Tphan]

I am using SBRIO -9606 + NI9694..  I don't have a scope right now but all data is read back from the hardware it self.  I am not sure the delay is real until I got a Oscope to check them.  It could be that the delay happen in the read back process.

Thanks

Tphan