FPGA Sampling Issue

[jer02342]

I am trying to run a cRIO 9045 with one 9229 and seven 9239 cards at 50kHz in FPGA mode. When I run the code with all channels, 32, the code will only run at a maximum of 25kHz. I've determined that the maximum number of channels I can run my code at 50kHz is 27; at 28 channels I max out at 25kHz. This is not an issue currently as I will only need to run 24 channels, but we are trying to figure out why we cannot run with a full load for possible future applications. We are using the calibrated mode, not raw (I still was not able to reach 32 channels with raw, but was able to run 28 channels). I am running a timing fifo as a U64 and converting the input data to SGL. Any help or tips would be greatly appreciated.

 

[ZYOng · Accepted solution]

The while loop of write FIFO could be the source of the delay. Try to disable that and if you can run at the maximum sample rate of 50kHz.

If Write FIFO is the source of delay, there are two ways to mitigate the issue:

1. Write an array of elements instead of a single element. You can configure the FIFO to write multiple elements.

2. Use pipelining. FPGA Pipeline Example

[jer02342]

Writing the multiple elements worked. Thank you