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FPGA output slow to enable?

I have a 14 slot PXI chassis with a PXI-1044 controller (1GB of RAM) and 5 PXI-7813R boards.  From LabVIEW FPGA 1.1, my FPGA code downloads and runs as expected.  I can use the controls on the FPGA front panel to change parameters and the FPGA outputs data.  I use the Digital Output blocks, not the blocks from the FPGA Advanced menu.

When I switch my execution target to LabVIEW 7.1 for Windows, although the "Open FPGA VI Reference" returns with no error, there is a very long delay before the FPGA outputs anything.  For the card in slot 3 it's > 2minutes.  For the card in slot 5 it's more like 10minutes.

As long as I only Close my FPGA reference (not Close and Abort) the long delay only occurs the first time I run the LabVIEW 7.1 code after a new download.  I can start and stop my LabVIEW 7.1 code after that and there is no long delay.  I believe the FPGA code is actually running during the long delay but that the outputs are not enabled.  I believe this because in my LabVIEW 7.1 code I have a timeout in my event structure which reads indicators from the FPGA every 100ms.  The FPGA is updating the indicators.

It seems like there is a timeout occuring on each FPGA card before the outputs are enabled.  I've looked in MAX under My System >> Software >> NI-VISA and I have no systems in the Remote tab.

Any thoughts?

Regards



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Greetings!

Thanks for the post. I shall look in to it further. There have been some known issues. Please look at the following links, they might be useful.


1) http://digital.ni.com/public.nsf/websearch/703440B5F67FADEE86256E16006D515A?OpenDocument
   http://digital.ni.com/public.nsf/websearch/3AA7E402EAEFEAE686256F4D001D0B35?OpenDocument
   http://digital.ni.com/public.nsf/websearch/0D8325309894115286256F3B00341159?OpenDocument


2) Consider Using the VISA Resource Name Input on the Open FPGA VI Reference Function for Systems with Multiple FPGA Devices—By default, the Open FPGA VI Reference function uses relative addressing. However, relative addresses can change. For example, if you have one FPGA device installed in your development computer, its relative address is 0. If you then enable remote finding for a remote system with additional FPGA devices, the address of the FPGA device in your local development computer changes.


Thanks and have a great day. We shall look in to the specific timeout issues mentioned in the email.
Best regards
Avi Harjani


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Greetings!

   Please let us know if you are able to resolve the problem or if the problem still persists.

1) Are you using the latest RIO drivers?
2) Were you able to reproduce the issue frequently

If you would like to test some more and make sure that -

1) Try writing to control and read from the indicator back (Something like a loopback). Also write to the same line and read back from the same line.

2) Generate the pulse train on the line and then look at the signal in a scope and verify if that is the signal you are expecting to

Essentially these are to verify if it is got to do with the connection / download from the host to the target, or the driver / hardware issue.


Thanks and hope this helps
Good luck
Avi Harjani

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1) Are you using the latest RIO drivers?
I'm using the drivers that came with the FPGA cards.  I'll have to check version numbers and reply back.

2) Were you able to reproduce the issue frequently?
Yes, and predictably.  As long as I simply "Close" the FPGA reference everything is fine.  If I "Close and Abort" (or reboot the PXI chassis), the problem occurs and the time for each FPGA card to enable outputs seems predictable.  As I mentioned previously, it seems that the download has occurred and that the FPGA is running because I can see the FPGA update indicators from my upper LabVIEW GUI (by polling indicators on the FPGA VI).

I still have to see if turning off legacy USB support in the BIOS fixes issues.

Because I have a handle on how to avoid the issue, I have other things I need to work on but I will look into this more after the hoilday.

Thanks,

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