FPGA single cycle timed loop (derived clock 1khz)

[jw121]

Hi all, 

I'm trying to make an FPGA vi that receives serial data with 1Khz frequency. So I used 'single-cycle timed loop', but it seems that the frequency that can be made is between 2.5MHz and 210MHz. 

Is there any way to receive data with 1khz frequency?

Thank you!

[Terry_ALE]

Which hardware are you running on?

[jw121]

Thank you for your reply!!

I have cRIO 9022

and NI 9234 

[Terry_ALE]

9234 is an analog device. I would recommend using a serial or digital device. Otherwise you are making more work for yourself.

Then you could check the example finder and see how it should be done.

[jw121]

Oh I was mistaken.
I'm trying to get accelerometer data, not serial data. 

So I made the loop proceed every 1ms as shown in the attached picture. But I don't think the data is being acquired at the right time. 

What is better way to get data with 1khz frequency? Timed loop or loop timer?

Thank you so much!

[Terry_ALE]

I would start with a shipping example.  Some of these devices have specific ways that things need to be run.  With AI devices sometimes if you do not sample at the ADC clock rate you may not be locked to the phase of the ADC and get noise.  You also may run into aliasing if you sample to low without a filter.

[ManuelSebald]

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@jw121 wrote:

What is better way to get data with 1khz frequency? Timed loop or loop timer?

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Hi

For an 1 kHz analog data acquisition you have to use a While Loop with a loop timer. 1 kHz is way too slow for a Single Cycle Timed Loop (SCTL). Second: you can't use an AI-device in a SCTL because they need more than one clock cycle (usually 40 MHz)  to acquire any data (digital-IO devices are usually possible).

Your BD looks right to me. In what scale does the timing not fit?

[jw121]

Thank you!!

Should NI 9234 only measure data at a fixed sampling rate (1.652 ~ 51.2 Ks/s) ? Is it not possible to measure with a frequency of 1khz?