Frequency Shift VI - FlexRIO FPGA DSP

[isoarsk4]

Hi everyone!

I am looking to use the NI PCIe-5785 for an application that requires outputting complex IF waveform from a single output connector. The NI support confirmed to me that this would be possible by using the DAC DUC, which combines the I and Q branches and translates the frequency up by 1.6 GHz.

At this point I am trying to understand the receiver/acquisition side. I would need to demodulate the complex IF signal into I and Q, which would be further processed in the host code. I understand most of the FPGA code in the NI-provided shipping example (Getting Started 5785), but the DSP VIs, especially the Frequency Shift VI, are giving me a headache.

As I understand, the Frequency Shift VI is supposed to translate the frequency up/down by the amount specified in the host code. However, I am not able to get closure whether this VI should perform the IQ/quadrature demodulation. From the block diagram I see that the input signal is placed to the I portion of a cluster of I and Q, with the Q portion initialized as zero.

What is confusing me is the description of the Frequency Shift VI. It specifies that both I and Q should contain a value produced by multiplying the input data by a cosine/sine. This would seem like IQ demodulation to me. In the provided FPGA code a zero is fed to the "data in.Q".

When I use the FPGA DSP functionality (freq. shift and decimation), I do not observe I and Q data in the host code. Instead, I am seeing (supposedly) the I component and zeros in place of the Q-component.

Does anyone know any details of the Frequency Shift VI? All of the DSP blocks are password-protected, so I am not able to confirm the functionality by looking at the block diagram. Also, if the Frequency Shift VI cannot be used for the IQ demodulation, are there any resources or examples for using the NCO VI in the FPGA?

Thank you!

[UMASO]

Hello, I would recommend you to test its behavior just placing it on a blank VI and connect any test singals and run it on host PC.  

The reason only I is filled and Q left zeroes is that single channel of PXIe-5785 can carry only a real signal.  If you have IQ signals coming from 2 channels of PXIe-5785, AI 0 should be placed to I and AI 1 should be placed to Q, assuming AI 0 corresponds to I and 1 to Q.  

[isoarsk4]

Hello,

Thanks for the reply! This is a good suggestion. I attempted to test the behavior of the freq. shift VI by using it separately in an FPGA VI, which is ran in simulation mode. I created FPGA frontpanel variables, which I can use to control the I and Q amplitudes. This way I am able to generate a complex waveform. I retrieve the samples to the host code, where I can plot them.

It seems that the behavior is the same as previously observed with our other application. The output I and Q signals seem to be copies of each other, but with different amplitudes. They are not demodulated from the complex waveform. I am still not sure how the equations match with the observed behavior, but I guess this confirms that I cannot use this VI for IQ demodulation.

[UMASO]

Hello, thanks for sharing your test code.  I hope it was helpful for you to separate a part of the signal chain and build a test code for the unit.  It may better desribe the effect of Frequency Shift to show input and output signals in frequency domains.  Since there is only a frequency shift, if you display both input and output signals in frequency domain, you would observe shifted frequency on both side of the original spectrum, if your input signal carries only I or Q component.  

Would you please check the following document which explains about DDC?  

NI PCI-5640R Digital Downconverter (DDC) Operation

https://www.ni.com/docs/ja-JP/bundle/if-transceivers/page/5640r/ddc.html

It is a document for an old device; PCI-5640R, but theory is the same.  Following your comments, I guess understanding DDC may help you to what is going on in the 5785 example.  Also, there are many articles which explain DDC, even on YouTube.  

[UMASO]

As for what is used inside Frequency Shift.vi, I remember the below two VIs are used.  

[isoarsk4]

Hello,

Thanks for the tips. I would say that I am fairly familiar with the concept of DDCs. I have also previously observed the frequency domain effects as you described.

In the link you provided, the NI-5640R ADC performs IF to baseband I/Q conversion, which is exactly what I am trying to achieve. Still, just to calrify, I wanted to understand if I could have used the frequency shift VI for this, because the equations in the VI's description hinted that it might actually do that. Based on this test it doesn't seem possible. Thanks for the help!

[UMASO]

Hello, PXIe-5785 example does almost exactly the same as NI-5640R.  

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@isoarsk4 wrote:

Based on this test it doesn't seem possible. 

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Which test do you indicate?  Do you mean you do not get an expected result from Frequency Shift.vi, and the result is different from what is indicated by the equation?

[isoarsk4]

Hello,

If I understand correctly, the NI-5640R performs something similar to the following at hardware level (figure from an article by Analog Devices)

I am under the impression that the NI-5785 does not do this, but instead the FPGA receives I samples from AI0 and Q samples from AI1. An NI support engineer informed me that I could transmit a complex waveform (mixed I and Q) from AO0 by enabling the DAC DUC option of the NI-5785. My intention was to do the same to the receive side, i.e., that I could demodulate the complex waveform looped back to AI0.

Before trying to implement an I/Q demodulator, I wanted to confirm that the frequency shift VI wouldn't already do this. The equations I am referring to are the ones circled in red here:

As the "data in.Q" is set to zero (i.e., only I data is used) in the NI-5785 example, I made the interpretation that the output of the VI could be the following:

I = I * cos(f_c)

Q = I * sin(f_c)

Where "I" would be the input signal from AI0 and f_c the center frequency of the band of interest. This would have been the same as I/Q demodulation (without LPFs), if I am not mistaken.

[UMASO]

Thanks for the additional explanation about your original question, and now I understand what you would like to accomplish. I agree with the NI support in that you can do demodulate signal from AO looped back to AI 0 and AI 1. Also, in the diagram you shared, the components in the pale-blue rectangular does exactly the same as what is in the receiver side of 5785 example.

I wish I had a time slot to make an example for you, but would you try the following?

As you did in your unit test code for Frequency Shift.vi, run the entire signal processing in simulation.

- for this, do not use actual signal from AI 0 (or AI 1), instead, transfer known signal from PC to FPGA.
- the known signal transfered from PC to FPGA is the one you would like to generate from AO
- the known signal should be the IQ which is upconverted on host-side in advance.
(you may use modulation toolkit or something)
- transfer back the results from signal processing back to host PC and see if I and Q are as expected
- the I and Q should be almost the same as the known signal before upconversion

By doing this, you can forget the entire of AO transmitter side and focus on testing signal processing only.

Once you have done the steps above, next step would be using real AI 0 and AO 0.