HDL Interface Node

[Ary]

Bom dia. Meu nome é Ary Carlos e sou estudante de Engenharia de Controle e Automação pela UFOP, no brasil. Uso o LabVIEW há mais de um ano e tenho uma dúvida com relação ao módulo FPGA c-RIO. Preciso realizar uma série de EDO's, daí decidi usar o ícone HDL INTERFACE NODE para chamar o VI com as equações (MATLAB SCRIPT). Mas há um erro identificado como ENABLE_OUT, o qual não consigo detectar. Peço ajuda o mais breve possível.

Grato.

[RyanB]

Hello,

If google translate is correct, it sounds like you are getting an error when using the HDL node in your LabVIEW FPGA target.  In order to allow for others to help find the problem, I would recommend sharing the following if possible:

1 - HDL source code

2 - LV FPGA VI with HDL node

3 - Exact error text & code

-RB

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Ary wrote (Google Translate):

Good morning. My name is Carlos Ary and I'm student of Control Engineering and Automation by UFOP, in Brazil. Using LabVIEW for over a year and have a question regarding the c-RIO FPGA module. Must perform a number of ODE's, so I decided to use the icon HDL INTERFACE NODE to call the VI with the equations (MATLAB SCRIPT). But there is an error identified as ENABLE_OUT, which can not detect. I ask for help as soon as possible.
Grateful.

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[Ary]

Hello. Thanks for help me. I gonna find what's wrong here and, later, I'll reply this message.

Ary Carlos