Has anyone implemented the SPI bus on a 7831R using Labview 2009? I

[smithd]

Thats the problem--I don't know what your slave device is expecting. Is your clock polarity high or low? In what order is your device expecting inputs? Take a look at this:

With FPGA, you just need to make sure things happen in the right order for the device. Is the fact that your starting array is preallocated to false causing a problem? Maybe in FPGA mode you only pull out 30 of the 32 bits, and the other remain false and cause the problem. It is difficult to be sure without extensive checking of your code.

[MorganS]

Hi Pete,

I made a few changes to your code which I think should help get things working.  This code assumes that your SPI device uses CPOL=0 and CPHA=0 (see the previous post).  I moved the read from the MISO line to the Set Clock state, since that line should have valid data at your clock's rising edge.  The slave device will also read at the rising edge, so the MOSI line needs to be set before that, in the Reset Clock state.  The Wait state was never called (from what I could tell) so I moved that functionality to the Reset CS state.  Also, it seemed like some of the clock outputs were reversed (but maybe that's because you're using CPOL=1).  Let me know if this works out.

Morgan S

Applications Engineer

National Instruments

[Eletrostatic]

Hi,

Just tested the code and it seems to only execute once for some reason. It also still multiplies the data by 2. I went back to test my old code just to make sure it was not a HW issue and this works fine apart from the fact the data is wrong when reading (Multiplied by 2). The SCLK should be active high in my design before and after clocking, its a requirement of the CPLD we interface too.  

[MorganS]

You're right about only executing once - I had the wrong state selected in the Reset CS state...it should go back to Idle now.  I've modified the code to work with CPOL=1 and CPHA=1, which would have the clock high before and after, but still read & write on the rising edge.  Is that correct for your device?  I also added an initialization frame just to make sure everything's in the right state when it starts.

Morgan S

Applications Engineer

National Instruments

[Eletrostatic]

Hi, First of all I got an "Domain error" when using the flat sequence with the SCLK, CS and MOSI. After putting these in the main state machine under "idle" the code compiles and executes. However the same issue persists. The data when read is shiffting my 1 place. 1=2, 2=4, 3=6 etc. Interestingly if I correct this with logical shifting by -1 it works fine until I reach FFFFFFFF then it overflows. I also increased the main clock just to make sure it was not an issue with this.

[MorganS]

Hi Pete,

Can you tell us a little more about your test setup?  Do you have your SPI device connected and sending/receiving known values, or are you just looping MOSI back into MISO, etc.?  You mentioned that the shifting isn't happening using simulated I/O (is that still the case?), so I want to get a better idea of the big picture.  Also, any details about the timing for the device may be helpful (like the CPOL and CPHA, which would be good to confirm).

Thanks,

Morgan S

Applications Engineer

National Instruments

[Eletrostatic]

Hi,

I was looping MISO to MOSI at the FPGA I/O. Simulation was fine but not at 5MHz, I tried . I now using the example shown on the first page of this discussion and its working fine. However I am now fighting with the DMA on the read part of the SPI port. As I want to transfer target to host on one of the channels. Problem is it is duplicating the data into the DMA somehow.

[MorganS]

Hi Pete,

I'm glad you were at last able to get the main SPI protocol working.  Could you tell us a little more about the DMA FIFO behavior you're seeing?  Is it duplicating every value, or is there any other pattern you can see?  Can you describe more about the code you're using to write data into the FIFO and read it back on the host (how many elements are you reading, etc)?

Thanks,

Morgan S

Applications Engineer

National Instruments

[Eletrostatic]

Hi,

I am trying to format my 8-bit elements from the SPI port driver to 32-bit before I put it to the DMA (target to host). But having some errors even I have fixed the array sizes. Any ideas what could be wrong here?! I am using a constant for the input value to the insert array.

[MorganS]

Hi Pete,

Instead of passing an empty array constant into the for loop and inserting elements, try using an Initialize Array with size 4 and then use a Replace Array Subset inside the loop.  This way the array will not change size.

Hope this helps!

Morgan S

Applications Engineer

National Instruments