How can I get 2 MHz on PXI 7852R derived clock?

[pbkelly]

I need a 2 MHz data rate on a serial data output.  I know in the FPGA I can use a Digital Clock Manager to drive another DCM thus getting almost any frequency, but Labview does not seem to support this.  I then looked for a flip-flop type logic element to divide the achievable 4 MHz clock by 2 and could not find anything.  This is a major element of logic programming, surely it is available?

PBKelly

[Spectre_Dave]

LabVIEW FPGA is a programming language - it does NOT have logic elements. 

See http://zone.ni.com/devzone/cda/tut/p/id/4799#toc7 for samples of digital communications code.

[srm@viewpointusa.com]

2 MHz data rate.  synchronous or asyncronous?  take your 4 MHz derived clock and act every other iteration.

[Ashwin85]

Hi ,

I have a similar requirement where i need to generate 2Mhz clock and CSB signal which will be low for 16 clock cycle and it has to go high on rising edge of 2Mhz clock.

I tried to generate these two signals using Timed loop but i get only default setting of 40Mhz clock and not other frequency .

Can any one help me to generate above signals.

I am using PXI -7852R
LV2010

Ashwin,

Labview user

[crossrulz]

From the project, you need to create a derived 2MHz clock (right click either on the 40MHz clock or the FPGA target, I'm not sure from memory which one).  You can then use that clock for the Single Cycle Timed Loop.

[pbkelly]

The clock manager in the FPGA is a dynamic device which limits its lower frequency which if I remember correctly is about 2.5MHz.  I ran a single cycle loop at 4MHz and used a shift register to have one period high and the next period low, giving the 2MHz frequency.  This also allowed me to synchronize other events to the rising or falling edge of the clock as needed.  By using a case structure with an integer as the selector and a counter shift register to count the cycles of the loop I was able to make a complex state machine that generated the proprietary serial protocol I needed.