How do I import multiple NGC/EDN as a clipnode?

[OlofK]

Hi!

I'm trying to import a design as an IP into a clipnode on a cRIO-9074 (with Spartan 3). The design consists of an NGC with additional IP as  subblocks in EDN and NGC format. I have included all files needed for building the FPGA in the XML description of the clip node and tried to build it in ISE, but it fails to build correctly when I compile the FPGA VI in LabVIEW. The build report contains the following errors.

Compiling vhdl file "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" in Library work.
ERROR:HDLParsers:1202 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 12. Redeclaration of symbol fx_delay0_data_i.
ERROR:HDLParsers:3010 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 20. Entity NiLvFpgaClipContainer does not exist.
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 24. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 24. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 25. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 25. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 42. Undefined symbol 'fx_delay0_clk'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 42. fx_delay0_clk: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 43. Undefined symbol 'fx_delay0_data_i'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 43. fx_delay0_data_i: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 45. Undefined symbol 'fx_delay0_ce'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 45. fx_delay0_ce: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 47. Undefined symbol 'fx_delay0_data_o'.
ERROR:HDLParsers:1209 - "C:/NIFPGA86/srvrTmp/GBG217~1.SE/WRAPPE~1/NiLvFpgaClipContainer.vhd" Line 47. fx_delay0_data_o: Undefined symbol (last report in this block)
-->

Total memory usage is 153900 kilobytes

Number of errors   :   14 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

These errors don't help me very much, and I'm starting to think there might be a bug somewhere.

//Olof

FPGA designer

[RyanB]

I have successfully used multiple NGC netlists inside a CLIP node.

The compile errors you list are often caused by mismatches between the CLIP XML and the IP because LabVIEW uses the entity and port names from the XML to instantiate the IP.  A few questions:

What is "fx_delay0_data_i"?  Is this a port on a CLIP?

Are you instantiating the CLIP more than once in your project?

Can you share any more info on your application (CLIP XML, entity names/ngc's) so I can help debug?

 -RB

[OlofK]

Thank you for the quick answer. After a break and some coffee I took a new look and it turned out to be a typo. Two labview port names pointing at the same HDL port.

I suppose this thread can be closed now.