How to set up my FPGA VI such that my IP Integration Node can be compiled at lower frequency than what can be derived through LV Project?

[SKTheLimit]

Hi Experts,

My goal is to execute my simulink model on LabVIEW FPGA. The target device is crio-9039. From my previous question, I have learned that crio-9039's lowest derivable clock is 4.69MHz. 

This is a problem because my code is much slower than 4.69MHz. I am guessing it will only run around 100KHz. However, because IP Integration Node requires to be placed inside of Single Cycle Timed Loop, I have to create clock of 100KHz. But again the crio-9039 can only derive no lower than 4.69MHz. (For CLIP it is the same story, as I need to specify 'clk' source to be selected from derived clocks)

I never thought utilizing slower clock is a challenge because usually we struggle fitting everything into fast clock cycles. Is there a solution to this?

Thank you in advance

[JKarma]

Hello SKTheLimit,

Based on the response in the first forum, I believe that this is limited from the FPGA at the hardware level. But with this leads me to another question, this test/code you developed it is possible to work it on the Real-Time Target?