IP Integration node input port data type as an array

[SMO33]

Can I have an input port as an array of std_logic_vector in an IP integration node?

I have this in my vhdl code:

type array_std_logic_vectors is Array (31 downto 0) of std_logic_vector (15 downto 0);

entity top is

Port (
      Clk_i             : in STD_LOGIC;
      Cmd_data_i   : in array_std_logic_vectors;

I am getting this error when I try to configure the IP block

Port "Cmd_data_i" with type "array_std_logic_vectors" has an invalid data type. The IP Integration Node supports only the std_logic and std_logic_vector data types. Refer to the LabVIEW Help for information about converting ports to these data types.

Is there anyway to make this work?

[dsFlux]

Hi SMO33,

As it says in the error message, the LabVIEW FPGA IP Integration Node supports only the std_logic and std_logic_vector data types for top-level VHDL files. See this KnowledgeBase article for information on converting VHDL data types for use with the IP Integration Node.

[SMO33]

I have read this article. It does show how to convert from one type to another but it doesn't show how you can do an array of std_logic_vector input.

Any idea how to work around this?

[WillD]

Make 32 inputs of std_logic_vector(15 downto 0)?

Make 16 inputs of std_logic_vector(31 downto 0) and massage the data in the VHDL, basically transpose.

Make 1 input of std_logic_vector(511 downto 0) and flatten the array as input?

etc...

[SMO33]

Making dicsrete inputs for the array is not practical especially I might need to increase the array size to 512.

LabView FPGA only supports maximum size of 64  std_logic_vector(63 downto 0)

[dsFlux]

Hi SMO33,

Unfortunately, you are not able to do an array of std_logic_vector. The workaround is what WillD is discussing in his post.