Implementing a MIMO controller on Compact RIO: fpga or realtime target?

[rsblom]

Hello fellow developers,

I'm designing a 4x4 MIMO controller foran magnetic bearing spindle. The controller is intended to operate at 20 kHz. Iwould like to perform the control design using Matlab (in order to be able to useadvanced control design strategies). The result of this design procedure will bea controller in state space form (of varying order, probably around 16). 


I have a CompactRIO setup consisting of a cRIO-9013 with 3M gatesand a cRIO9014, 128 DRAM, with 2 GB on chip storage, that I would like to use toimplement this controller. I'm wondering how to proceed with this, as I understandthat in principle I have two targets for this controller, the FPGA

and the Realtime processor. Which way to go?

Implementing it on the FPGA would require transforming this controllerto a fixed-point form (I really have no clue how to do this, should I use the DigitalFilter Design TB for that?...). I expect that the result could be quite attractivein terms of performance. It seems also interesting as it leaves the processor availablefor other tasks, such as (intensive) data logging. But is it really a viable option....?


Implementing it on the real-time target is directly possible (floatingpoint no problem) and only requires the FPGA to pass on the I/O data (right?). However,will I be able to reach a sample time of 50us with the above hardware? 
 


What is the best route to pursue? I appreciate your assistance!



NB, I'm using LV 8.5 
 


Rogier Blom


Delft University of Technology
- The Netherlands

Message Edited by rsblom on 08-24-2009 06:08 AM

[ninlmartijn]

Dear Mr. Blom,

thank you so much for your post on our webforum.

With the FPGA target you can run multiple processes true parallel, so in my opinion this is ideal for multiple inputs multiple outputs control. The FPGA can give you nanoseconds response. The delaying part in your chain would be the IO modules (for example; it takes time for a input module to convert from analog to digital and for a analog output module to convert from digital to analog). You can't use the control code you mentioned on the FPGA; you have to implement this control algorithm with Labview VI's which can be used on your FPGA target. If you create a VI under the FPGA target all functions which can be used on this target will be available on you functions palette.

You are correct that you can't use a floating point on the FPGA target. But don't be afraid for Fixed point. With an analog IO module you can chose for raw data or for Fixedpoint. When you chose for Fixed point it will be directly the correct configuration. The same counts for the output module. You can always configure your fixed point control / indicator or constant (properties, datatype). There you want to use it in signed / unsigned and important the integer word length. For example I'm measuring within the range from -10 till + 10V. Total range is 20, so I need 5 bits (= 32) to cover this range. The total word length decides then how big the steps are that you will take (if I chose also 5 I will takes steps of 1 since all bits in the word length are for the integer numbers). If you choose 6 bits the steps are 0.5; 6 bits total, 5 bits for integer word so 1 bit is left. I hope this clarifies the fixed point math a little bit. Please refer to the Labview help file for extra information. At the (real time) host VI you can easily convert the fixed point to a floating point (there are conversion functions for this at the numeric palette).

With implementing the control part on the Real Time controller, you are able (when using the Labview 2009 version) to implement the advanced control design strategy you talked about. There is a Mathscript realtime module to do this (since LV 2009). But again; FPGA offers you true parallelism.

I hope this will bring you further in deciding which way to go, please don't hesitate to contact us when there are any further questions. WIth www.ni.com/netherlands you can find the contact information from the local Dutch office.

Best regards,

[rsblom]

Dear Martijn,

Thanks for your extensive reply. I might as well contact the NI office for some more detailed questions, but for the benefit of everyone else here, allow me to continue the thread a bit.

Indeed, the FPGA solution seems quite attractive and I must say that going to fixed-point itself doesn't scare me. I have two basic concerns, and besides I don't see exactly how to solve the practical side of it. Let me clarify.

My first concern is the risk of getting into scaling problems. The outcome of my control design procedure in Matlab is simply going to be a set of A,B,C and D matrices of appropriate dimensions, representing the controller in state-space. The elements of these matrices are likely to vary to a large extent. More importantly, how will I be able to make sure that during operation the calculations themselves stay within the range of the fixed-point representation? I have observed that in the digital filter design toolbox there are routines available to break up an arbitrary siso filter into second order blocks, each which is correctly scaled - quite a common procedure for digital filter implentation. However, such a routine is obviously not applicable for MIMO state space filters. 

Obviously, transforming the controller into some fixed-point representation will introduce some error (I assume). How will I be able to calculate this? I have read about simulating the FPGA controller, together in Matlab, etc., but what I would like to see is simply the difference of the frequency response of the controller in floating and in fixed-point representation. Any hints how to do?

Then the practical side: it doesn't seem like a smart idea to hard-code the controller (after some manipulations to get it into fixed-representation) onto the FPGA. The FPGA palet doesn't offer much flexibility here. What to do? Is there a conversion tool available that generates FPGA code (like the Digital FIlter Design Toolbox does for scalar filters)? 

Thanks again,

Rogier