01-04-2010 10:38 AM
Hi,
During my project I have been building a data logger with a cRIO-9014. The FPGA samples 11 input signals at the rate of 640 Hz, ie 7040 data point per second and continously writes to a DMA FIFO. On the RT Target I got two timed loops, one for reading the FIFO(high priority) and the other for communicating to a host and saving the data to the internal hard drive. The two loops got the same period time of 200 ms and are reading 1408 samples per read, the same number as the FPGA is writing to the DMA FIFO per 200 ms.
The problem is that the CPU usage is totally random at the start and from that point increasing at a certain rate. At one point the total CPU usage started at 29.6% and after four hours the CPU was at 98% The timed structures are using almost all CPU, see attached picture.
The timing is crucial and when the communication timed loop(normal priority) finishes late I will miss data!!
I attach the code for my project.
01-04-2010 11:56 AM - edited 01-04-2010 11:56 AM
Hello bela6423,
Out of curiosity, have you seen the loop actually become late? Even if you haven't, I agree that kind of CPU usage growth is cause for concern.
One thing to try, avoid using build array inside the loop. See http://zone.ni.com/devzone/cda/tut/p/id/4715 for details. The big reasons for that is determinism, but it may help with what you are seeing and is a good practice in general.
Let me know how it goes,
Sebastian
01-04-2010 04:37 PM
The left data node got the Finished Late? [i-1] functionality, which I am using in both timed loops. The high priority timed loop only finishes late at the first iteration. The normal priority loop on the other hand misses when the CPU usage is high.
Yes I should initialize the array outside the loop and then with replace array put all 1D arrays at the right place to avoid allocating memory at the wrong time. But I don't think that is the problem with the growing CPU usage for the timed loops!!??
01-05-2010 05:32 PM - edited 01-05-2010 05:33 PM
I think you are correct to be skeptical given the symptoms, but it is probably still worth trying.
Otherwise, can you isolate it to one of the two loops? Does the cpu usage growth still manifest itself if the high priority loop is disabled?
What about if the timed loops are replaced with while loops and timing vis?
Sebastian