Issue with line direction on NI 9401; no output when 'run as startup' only when running VI in dev env

[robdevyogi]

Hi,

I have a FPGA vi that is doing some I/O on the NI 9401 modules I have installed in a cRIO-9402/cRIO-9102 (1M FPGA 8-slot chassis) system.  I have configured some of the modules for both input and output.  However, it seems when I reset the cRIO and the VI runs at start-up, it doesn't generate any outputs, though it does process the inputs. Any ideas?

On the other hand, when I run the VI while the cRIO is connected within the project, either runnig the FPGA vi by itself or if running the toplevel RT Host vi that starts the FPGA VI, it seems to work fine.

I have set the initial line direction correctly in the module properties for the NI 9401 and I have also tried to manually use the FPGA I/O methods to set the line direction correctly once the FPGA VI starts.

I am running LV2010, RIO 3.5.1. Win XP.

Thanks,

[charris]

Rob:

Would you be willing to post a shot of your FPGA VI up? I'm specifically curious about the I/O methods and line direction config.

[robdevyogi]

Hi Caleb,

I've included the portion of the FPGA VI where the signals are read and where they are set.  The whole VI is basically just a while loop with TRUE wired to continue terminal. And then there is a statemachine that processed the inputs and then generates outputs.

All IO modules are NI 9401. The odd numbered modules are configured according to ni9401_odd.png. and even modules are configured to be output only.

Module setting for odd-numbered modules. ni9401_odd.png

[PaulRB]

Hi Rob,

Instead of setting the direction in the project, have you tried setting it dynamically in the VI? Before you enter your main loop (in the FPGA VI), you can use the "Set Line Direction" method. Give this a try and see if it works in your startup exe.

[robdevyogi]

Hi,

Oh yes, I should have mentioned that. I did add that as a way to fix the issue, but it didn't make any difference.  What is below is all in a VI that is executed before the while loop of the statemachine mentioned previously.

[charris]

Rob:

If you go to the example finder and open the 9401 examples (Hardware Input and Output --> CompactRIO --> Module Specific --> Digital Output), do you have the same issue? Your code looks okay based on the screen shots, but I'd like to rule it out for sure by replicating the problem with an example.

[robdevyogi]

I built the example for my backplane.  When I run the FPGA VI it works as expected.  However, if I create a RT VI it doesn't work (or maybe it did work once or twice only when I first tried?...).  If I launch the RT VI automatically on startup then it doesn't work.  I also tried to swap the NI modules without any change. The backplane I used to run this example was a 3M FPGA 8-slot backplane (cRIO-9104). Feel fre to try the project that I have attached and see if it is possible to have it run when you power up the system.  It currently toggles the output on DO5 (which is performed by the RT host vi).

[charris]

Rob:

The default value populates the control for line direction on the FPGA VI (at least, it does in the example you posted). The default value is "no change," which will leave the module in its default state when it starts up (which is input). The description in your first post validates that: the VI processes inputs, but does not generate outputs. Was your original FPGA VI hardcoded to switch the line direction to output on startup?

I'm also noticing that your RT VI isn't activating your "Change Direction" control. Without switching that to "True," we'll never restart the outer FPGA while loop, and we'll never set our line directions to output. My guess is that the FPGA VI starts up and passes over that code before the RT VI has a chance to set the control values.

To fix that, you can configure the FPGA reference to not run the FPGA VI when called, then call a reset method, write the direction control values, then call a run method afterward.

Alternatively, you can put a read/write control method for the "Change Direction" FPGA control. That will simply iterate the outer FPGA while loop, causing it to inherit the current state of the host line direction controls.

If you're not sure if the main FPGA while loop is cycling over, you can also wire a boolean to the FPGA LED as a diagnostic indicator.

Another thing you might want to consider is putting your input/output DIO code in two separate cases instead of together in the nested while loop. That way, we're only calling the code we need to.

Hope that helps out!

[brian_d]

Where is the Set Line Direction method located? I have 2 NI 9401 modules but am unable to find it.

Thanks,

Brian

[Allison_M]

Hi Brian,

You can do this using an FPGA I/O Method node, right-clicking the method node and selecting Select Item>> FPGA Target >> ModX (where X is the module number). Make sure you select the whole module and not just a DIO line. You then should be able to right-click the method node again and select Select Method>> Line Direction. This will allow you to set the Line Direction by nibble.

Hope this helps,