12-12-2005 12:43 PM
12-12-2005 03:08 PM
12-12-2005 03:18 PM
Hi Stephan,
Thanks for the response. Is it possible to get the sample code that you used? I tried many different block sizes for the DMA FIFO (from 2K to 64K) and also different sizes on the RT side. I am confused as to what is the best combination. Maybe I was making my FIFO too big? At some point I just decided to keep it at 32K on the FPGA and
I thought I was doing 16 bit numbers but maybe they were actually 32 bit? I'll have to go back and check.
Also, have you done any streaming to a file for an extended time with the new DMA features?
In any event, I would love to get my hands on the sample code you used :)) My boss would also be happier, which might lead to more sales for NI! 🙂
My goal is to prove that I can use the cRIO as a psuedo high speed, long term data logger (within storage limits of course). I am close to that now. I am making the argument that I can drop a cRIO into any test system that currently uses a PLC/PC combination and it will be able to do everything plus much more without having to buy a PC and PLC for each system.
Overall I'm very pleased with the cRIO performance difference by just moving from LV7 to LV8.
Any help is appreciated!
Jeff
12-12-2005 04:01 PM
12-12-2005 04:08 PM