I have a project that relies on VISA serial functions to acces two serial ports on the mezzanine-board of an sbRIO-9607. The FPGA dummy VI (bland FPGA VI) used to get that functionality is referenced at the top level to ensure that the bitfile is loaded on the FPGA as long as the RT application is on the RT target, and this seems to have worked fine before: I make an image of an sbRIO-9607 and use that to deploy it to others *without* having to include a bitfile. This seems to be a supported method according to Method 1 in the document Managing FPGA Deployments
I recently updated this project from LabVIEW 2022 to 2025Q3 (for Windows) though...The application and FPGA build was recompiled after the update as always etc, and the RT application ran as expected - but I later found out that VISA writes would fail...(inits would not report any errors, but writes would) and the fix was to download the bitfile manually to the FPGA.
The question now is, why was that suddenly required? The RT application using the VI Reference method was running on it, should it not have included and loaded the bitfile on itws own, just as before? Note that no changes were made to anything on the project or VIs here, no config changes, no code changes... it was just opened in 2025 built (FPGA build included) and deployed with no changes...So I would expect it to work the same way (I at least have believed it to work) in 2022 and earlier...Or is there anything in this method that is a weakness here, or that change din 2025?
