Multiple resources between cRIO and host

[Mike1]

Hi, I am trying to use the 9401 digital I/O module to perform simultaneous operations that run on two differently timed loops.  Ultimately, I am trying to place a sonar sensor on a servo motor and have the servo move at a specified rate while the sonar scans continuously.  I am able to compile each program separately using different fpga programs and have them function with the host independently, but how do I join the programs?

1. Can I have the host program open two different fpga references?  In this case, I would want two differently timed loops for each reference.
2. Or do I have to have the fpga program contain all of the I/O’s and open the host program with only 1 fpga references?  I have been able to get the function to sort of work in this case, but the host ends up sampling both operations on the slower clocks sampling rate.

Please let me know the best way to handle this.  I have been searching on the examples and amazingly have not seen one where two different operations need to be performed with different clock rates.  (They do not need to be synchronized). 

Thanks!

Mike

[Prashanth]

Hi Mike,

When a FPGA vi is compiled and the bit stream is downloaded on to a FPGA hardware (such as a c-RIO), the hardware takes on a personality determined by the code in the FPGA vi. NI FPGA hardware cannot have more than one vi (bit stream) run at the same time. Hence, to achieve the same functionality one would have to integrate code from all the different FPGA vis into a single vi (parallel loops). Compile the integrated code at the fastest clock rate possible and then place loop timers in each of the loops to control the loop rate.

Hope this helps!

Regards,
Prashanth

[Mike1]

Thank you for the information.  We have tried to do that with two differently timed loops on the host application (as shown).  The host will run both the sensor and the motor, but both objects will run at the rate of the slower timed loop.  (Essentially the faster loop rate is ignored).  Do we have to put the clock rates on the fpga program, or on the host program?  Perhaps the code for the host program is incorrect?  

Thanks again!

Mike 

[Prashanth]

Hi Mike,

You have to place the waits in the loops of the FPGA vi to control how fast you are acquiring/outputting data on your actual FPGA hardware. Once the data is in the hardware you can process it any way you want. For example, you can make decisions in the FPGA vi itself and make changes to your output data on the FPGA hardware. Or you can pass the data back to the host program and deal with the data there.

Also, here are some links to some awesom FPGA training material. This is the first place to go to get familiar with LabVIEW FPGA paradigm. Hope this helps!

LabVIEW 7.1 FPGA Module Training http://zone.ni.com/devzone/conceptd.nsf/webmain/62B388DB80B557028625703700639B89

Developer Zone http://zone.ni.com/devzone/devzone.nsf/webcategories/94DB088AB1BCDF4E86256B7A0051352E

Have a great day!

Regards,
Prashanth