New to cRIO, compiling concerns.

[d.gelman]

Hello,

I have a cRIO-9024 and I am having issues understanding how to comunicate with it.  I have multiple modules attached (9505, 9501, 9403 .. etc), I have learned that to control 9505 and 9501, I must using the FPGA target.  I see the instances in my project window and I can drag them into my block diagram, but I am having troubles compiling any sort of simple program.

For example, I tried putting a control (T/F) into a DIO of the 9403 and this simple program wont even compile.

When I say, wont compile - it takes >5 minutes and does not finish.  I don't think this is normal so I cancel compilation.

Is what I am doing correct?  

Daniel

[Chris_Jones_NIUK]

Hi Daniel,

Compile times are dependent on the performance of your compiling PC, as well as the size and complexity of your FPGA code.

However, compile times will in most cases be over 5 minutes. If you are still facing issues after leaving the FPGA code compile, please let me know.

[d.gelman]

Yes definitely, I realized that the high compile times (upto 12 minutes) was probably due to using a 5 year old machine.

Yesterday, I purchased an i5 with 6Gb of RAM and I am currently installing the Premium Suite. Hopefully this machine will cut down the compilation time significantly.

I am new to cRIO/RT Interface Target/FPGA Interface Target.

Please let me know if I understand.  The basic startup modules (9403,9205 and the 9263) can be run from the RT interface which allows the control of these modules strictly from the controller embedded in the cRIO.  To utilize the other modules like the 9505 or 9501, the FPGA in the chassis must be used - which communicates with the controller to allow the compile (in turn, increasing compilation times).

If I am missing anything please help me understand.

Thank you,

Daniel

[Chris_Jones_NIUK]

Hi Daniel,

It's worth noting that all modules within the cRIO chassis will communicate through the FPGA backplane to the RT OS on the controller.

When 'not using the FPGA', this is known as scan mode and what this does is (still physically through the FPGA backplane) read or write values to/from a table which is also read/written to by the RT OS. This allows easy and quick access to the I/O, but has the limitation of update rates (scan rate) of 1KHz.

The benefit of defining a custom FPGA vi to run on the FPGA backplane is that you can access I/O speeds from modules exceeding 1KHz. You can also perform simple processing tasks on the FPGA to free up controller resources.

In order to run a 'VI' on the FPGA backplane, this must first be complied into a 'bitfile' for that particular FPGA. This is a resource intensive task which will take place on the development PC only (unless an external compile server is defined). The controller has no effect at this point.

With regards to compile times, 12 minutes is not generally considered a high compile time. For prototyping your FPGA VI, you have the option in the project of running this on the development computer with simulated I/O (right click the FPGA target in the project explorer window). This will allow you to make small changes without the need to recompile. Once you are happy with your FPGA VI you can then compile this for the FPGA target and deploy it. A recompile will only need to take place when changes are made to the VI.

This page provides a number of link to useful information related to the architecture and use of the cRIO.

I hope this clarifies things a little.