PID (FPGA).vi Gain Scale Question

[bones349]

Hey Guys,

Im using the PID (FPGA).vi in LV 8.5.  Two questions:

The T(s) sampling time parameter.  I have the value set in the properties at 10 uS (100 kHz), the loop it is in runs at 160 KHz, so what rate does the VI actually use?

The second is the scaling of the parameters on the Host side.  I have been using the "niFPGA ScalePIDGains.vi" found in the "Using Discrete PID - R Series" example.  This is fine and dandy if you are using relatively large time periods, (> 0.01s).  However, in the system I am controlling, I've realized that an Integral/Derivative time in the 1-100 uS range would be beneficial.  How do I change this scaling VI to allow for these small values?

There is a seperate T(s) value used on the host for the "niFPGA ScalePIDGains.vi".  Should this value match what you have compiled on the FPGA, or can you use this to change the scale you are working with?  I've just been using the default 0.1s up to now, but now realize I need the smaller values.

Thanks!!

[JeffL]

Hi bones349,

First question: Where are you getting the 160 KHz number? It seems quite slow if that's your FPGA loop rate. What controller are you running?

I believe all the T(s) should be the same. This is what they do in the example you refer to.

What is the time (>0.01s) you are referring to? You mean the TD/TI values? Why would smaller values not work?