RT and FPGA code linkage

[Keith GD-AIS]

I have a sbRIO program that I built and the FPGA code basically scans multiple inputs of a 9870 4 port serial port card for the RIO for a query.. Once I get bytes at port (query) I send them to the RT program for processing. The RT program generates a response to the query and sends those bytes back down to the FPGA  to get transmitted as a response to the query. The response needs to be in sink with the query. The problem I have is when the RT and FPGA code are deployed I get an occasional out dated reponse, I have tried changing the timing relationship between FPGA and RT code, but I can only seem to make this issue worse and not better. Data is being passed back and forth over the control block (controling indicators and controls) between the FPGA and RT.  When i run this same program without it being deployed, basically running my development code from the PC, I do not see this issue - seems to only be an issue when I fully deploy the RT and the FPGA code.

   Thanks,

  Keith Calhoun

[StephanieA]

Hello Keith,

I'd like to get a bit more information about your application. What do you mean by outdated response? Are you getting any errors? You also said the outdated response occurs occasionally. How often does it happen?

How are you sending data from the RT exe to the FPGA? Are you using FIFOs? Read/Writes?

[Smootastic]

How are you synchronizing the RT and FPGA code?  Interrupts may help to further synchronize the two sets of code:  http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgahosthelp/synchronizing_using_interrupts/

[Keith GD-AIS]

By outdated repsone I mean I got the previous query or commands response (stale data). Basically every query/command read in by the sbRIO code gets passed up to a program on the RT that performs a process on the data and generates a response. That response is then passed back down to the FPGA and sent out on the serial port as a response to the current query or command. Ocassionly I get the stale data back - it seems radom but it occurs every 10-15 queries/commands. The queries/commands are occuring approimatley every 15 milliseconds and are continuous as they are part of a polling/status routine.

[StephanieA]

I'm still looking for some clarification as to the protocol you are using to pass data up to the RT host and then back down to the FPGA. In your code, are you using FPGA Read/Write VI? FIFOs? Interrupts? If you are not sure what method you are using, you can use the context help to get the name of your VI or if possible, post a screenshot/portion of your code that is causing you problems.

[Keith GD-AIS]

Stephanie O. - Sorry I didn't go into more detail on that. The data read in by the FPGA code is written to an indicator. I use the read/write control function in the RT to read in that data for processing. I then use the read/write control in the RT to write to a control (after the data is processed) in the FPGA - and then the data populated in the control is what gets written back out of the serial port as a response to the query. I am 99.8% sure that this issue has been resolved by implementing an IRQ in the FPGA code in a sequence frame after the query has been read in and written to the indicator. I then placed an acknowledge IRQ in the RT code after the data has been processed and written to the control down in the FPGA code. My over all link is not running totally clean yet, but I believe that might be due to data being buffered in another set of hardware in the loop. Thanks for your help with the problem I was having with the NI code. Keith Calhoun