Read more elements from a DMA FIFO than Number of Elements

[Steffan]

I’m figuring out how to transfer data from an FPGA to the RT-target. A FIFO seems to be a good choice.In an example application that came with the hardware I studied the concept and experimented with it. The number of elements of the DMA FIFO is 1023 but I find it strange that on the RT-application I am able to read 2000 samples at a time. The example works fine so how is it possible to read more samples than the size of the FIFO?

[dwisti · Accepted solution]

There are 2 FIFO's, one on the FPGA and the other on the host.  The FPGA FIFO is limited to 1023 elements.  The host FIFO can be much larger. The default size is 10000 elements.  The DMA is considered full once both are FIFO's are full.

[Rick_F_Foster]

How is the size of the FIFO on the RT side managed? I see that on the FPGA side, it can be set in MAX.

Rick

[dwisti]

MAX is not involved with FPGA DMA FIFOs. The FPGA DMA FIFO depth is set at development time.  The host side (not necessarily RT) depth can be managed with the configure method.

See this link for more info.

[Rick_F_Foster]

Thanks, I see how to use the configure for the RT side now.

Rick

PS: I meant to say I used Project Explorer, not MAX to configure the FPGA side FIFO  😞