Running the plant model (e.g: Transfer function block) in CRIO host VI

[CW81]

I am trying to program a Smith Predictor architecture control system in CRIO

What I DID:

Use the simulation loop instead of timed loop in the host VI, so that I can use the transfer function block in the host VI. To program the smith predictor architecture, I need to have a plant model parallel with my actual plant (SERVO motor). However, when I ran the program, the transfer function block output me a "NaN" Please see the attached screen shot.

SO, have any one tried using a transfer function block in the CRIO host VI, OR has any one know how I can insert a plant model in my host VI using other method instead of using the transfer function.

Thank you 

Cheers, 

CW 

[BCho]

Hey CW,

Awesome job with the screen shot and the probes. Taking a closer look at your probes, you are likely getting a NaN from your transfer function because the input to your transfer function block is also NaN. So, the output from your PID vi is NaN. At this point I am not sure why the PID loop is giving your NaN; but this is probably the reason your transfer function is giving you NaN.

[CW81]

Ben, thanks for the hint.

The PID is outputing the NaN is due to the transfer function output. When I probed it, the intial value for the output to PID is a integer.However, after one loop where the first feedback start getting back to the controller (that's when the "NaN" from the transfer function feedback to the PID block) causing the PID output a NaN value after the first feedback loop. 

Thus, I am trying to figuring out how I can put in a plant model in my CRIO host VI. The simulation loop runs fine in the CRIO host VI but just that the transfer function block is not giving me the right output.  

[BCho]

Hey CW81,

Since you have the rest of your simulation loop running fine, perhaps you can isolate the transfer function portion of your simulation loop. What happens if you run a simulation loop with nothing but your transfer function? One situation where you may get a Nab (not a number) is if you attempted to take the square of negative number. So, maybe there is something is the input from your PID.vi and your transfer function that is cause the transfer function.vi to try to take the square of a negative number. This may be one thing to look at.

Knowing a little more about you system could help other try to recreate the behavior your seeing. What is your transfer function? How do you have your transfer function set up? Perhaps you could break down your code to just the PID.vi and the transfer function, leave out the working FPGA code, and post the simpler routine. What solver are you using with your simulation loop? How do you have the simulation loop set up?