SBRIO 9606 bad clocks or bad program

[Tphan]

Hello all,

 I  used the Labview FPGA to create a very simple clocks out put and monitor it using  both method.  They are 20Mhz, 10Mhz and +/-5Mhz

-Internal loop back: monitor out put directly clock waveform from the source

-External loop back monitor: Wire the output port to the input port and monitor it.

In both case I am seeing bad random and clocks signal and .  It does resemble of clock divide but not consistent.

I  rather new to the FPGA stuff so the question is did I do some thing wrong or I just has a bad SB-RIO?

Thanks

Tphan

[nanocyte]

A few suggestions:

• Post the VIs or snippets instead of an image. That will help us try and reproduce the issue over here.
• You're not monitoring timeouts. You should track them with something like this
• It is possible for there to be some small (tens of nanoseconds) of jitter and synchronization issues. They are described here:https://www.ni.com/en/support/documentation/supplemental/11/rio-mezzanine-card-digital-i-o-capabilit... but you should only see that on ReadIO if anything.

[Tphan]

Thanks for replying.

Sorry for post too much than needed.  I just want to see if I can show details. 

I look at the white paper and it seems like the maximum skew time was 19 nS but that was for DIO to DIO and it only reduce the pulse with a little and should not be affected the 5Mhz signal clock like the pulse width wild changes as much as 2 times.  What I also see is the divided clocks was not synchronize with each other as if they are coming from different clocks sources. Also it can withstand up to 22 Mhz  signal.  some of my clocks are only 5 MHz

I try the snippet you show me and indeed it was time out.  How ever after investigation a little more.  The time out actually is the result of the FIFO buffer was full and the data was written to the buffer too fast because this is a Single Time Loop Execution. It practically writes to the FIFO at frequency 40 MHz.  So I decided to add add a little code to only captured a number of samples as below.

This prevent the timeout completely but I still got very bad clocks cycles event at 5 MHz clocks.

 I decide to try on the C-RIO-9033 with the NI-9041 digital modules and I got perfect clocks reading as below.  And they are synced with each other. It even surprised me that the maximum clock out put for the NI-9041 is limited to 20 MHz if I use 1 output.  For 4 outputs the limit will be 20/4 = 5 MHz.  So the NI-9041 goes beyond the spec.  How ever I can't concluded that the SB-RIO 9606 has a bad clocks or simply need more complex code to generate a clean clock signals.  

Thanks

Tphan

[Tphan]

Sorry the FIFO should has been a False case not the True case

Tphan

[nanocyte]

Please post VIs and snippets instead of pictures of code.

You mentioned "very bad clocks cycles event at 5 MHz clocks" is that on Loopback or the Read?  Have you tried checking the signal with an O-Scope?

Your "Get Number of elements to write" logic is going to randomly cut out the stream so it's no longer "lossless". You might want to consider maybe code to latch the "low buffer" condition so that you can detect that and end the "acquisition" on both the FPGA and Host.

[Tphan]

Both Loopback and ReadIO has the same problem.

[Tphan]

Updated story.

I  modify the code to be a little bit more complicated.  Adding a control so I can disconnect data feed to the FIFO.  That way I can fill the FIFO and then read them pieces by pieces from the Host.  It turn out I have perfect clocks signal over the 32767 samples.  How ever after that the samples become erratic with changing pulses.  Turn out it is related to the FIFO size.  I requested 20000 sample but the FIFO assigned 32767 samples.  The strange thing is from the Host side, the remaining size is 65535.  That is  much bigger than requested.  And it seems the remaining sample does not coming down less than 65535 until read out 32767 samples.  But after that all the samples just junk data and inaccurate.  I guess the moral story are:

-Bad program

-Do not over fill the FIFO

-The "Get Number of Elements to Write" function is not accurately reflecting the remaining  space of the FIFO

Thanks every ones

TP