Stream Digital Output Array of Stored Data using FPGA

[Acer]

I am evaluating the options for being able to have a large digital dataset stored in memory (somewhere on the FPGA), to be sent out up to 2MHz.  In essence, a digital vector generator that has the vectors located on memory so it would not need communication with a Host, works on power up. 

So the requirements would be:

1. Digital Output up to 2MHz rate
2. 3 Lines: CLK (to FPGA), RX (to FPGA, only used to receive a Sync Command/Signal for TX line), TX (from FPGA) 
3. The TX data stream would need to be able to store/send 5 million lines of 8 bits

The thought was to use a c-RIO with the 9402 module.  Any other ideas as far as hardware, or better yet, the software implementation technique to go about.

Thanks much, K

[WishKebab]

Hello Acer, 

If you have to store 5 million lines of 8 bits, you are looking at 40 million bits = 5 MB + overhead of storage.  If you want to stream that from the FPGA block memory, our Virtex-5 FPGA hardware is not likely to have enough space.  The largest Virtex-5 chip we offer is the LX110, which only has 4.6 MB of memory available.  

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/Virtex-5_LX_Product_Table.pdf

Some of our newer FPGA hardware uses the Kintex-7 family of chips, which offer ~34 MB of memory.  It may be possible to do what you ask with one of these.

The cRIO-9068 has an Artix-7 chip, with 13 MB of memory, so it may be possible with that, but it's hard to say how much memory will be used by other applicaiton areas and general overhead.

http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

2MHz per channel, over 8 channels, means you are looking at 16MHz total bandwidth, which is likely not possible to stream from the RT side to the FPGA.