Synchronization issue between FPGA and RT loop on host

[dotadk]

Hi there,

This is a newbie question. I'm using the following hardware: 

cRIO 9025

AI module 9223

AO module 9269

The application has 4 parts:

1. compute some values and insert into an array

2. send the values one by one on the AO module, using the FPGA. 

3. read the values one by one on the AI module, using the FPGA. The values are sent to the host using a FIFO. On the host side a Timed Loop reads the values from the FIFO and puts them in another array. The loop should end once a "reading stopped" signal is received from the FPGA.

4. once the transfer is complete, perform some post-processing. 

Parts 2 and 3 run in parallel. I'm attaching screen dumps of the host.vi and fpga.vi. I've removed parts 1 and 4 for simplicity. 

Unfortunately, for some reason the Timed Loop in the host (the one reading from the FPGA) does not stop. Looks like the "reading stopped" signal doesn't go through.

Anybody can please explain me why this happens? Or how can I fix it? 

Any help is appreciated. 

Thanks!

[BillTür]

So you are setting the start sampling to false after the input loop stops. The case structure on the FPGA will the execute the false case where you don't write to "stop reading" I suppose? Maybe put the local in the lower loop on the FPGA and put the control in the top one. The control is not executed when start sampling is false, thus you won't have a new value at your local. If you know what I mean...

Hope this helps..

[dotadk]

Hey BillTur,

Thanks for the reply. I assumed that the FPGA case structure will change to the FALSE case only after the code inside the TRUE case will finish executing, thus after stop reading was set to true.

I've reorganized the code, but now a strange thing happens: although I initialize the FPGA stop writing control to false, the first time I run the FPGA.vi, the control is set to true. As such, in order to make the code work, I have to:

1. Run the FPGA.vi, reset manually the controls, and then stop. 

2. Run the host.vi. It will work ok, I still have an issue with synchronizing the start of the reading, so the first 10-15 values that it reads are not the ones I send,

3. a. If I run the host.vi again, the cRIO get unresponsive. I need to unplug the cRIO. 

    b. Running steps 1, then 2 will work. 

I'm attaching the screen dumps of the two VIs. 

Any suggestions are more than welcomed. 

Thanks!

D

[BillTür]

Can't currently find the source of this behaviour. Maybe try simulating on development computer to find it, you will have to disable the input and output nodes though.

Is it possible for you to do it another way?

My thoughts:

- Use a FIFO to send the values to write to the FPGA, send all of them at once (in an array)

- Read all the values coming from the FPGA at once (don't know if this maybe is impossible in your application)

- trigger the write loop on the FPGA by checking the elements remaining in the FIFO coming from the host

- end the loop by checking if it completed a fixed number of iterations (and has read from the FIFO during those)

- trigger the read loop with these booleans (rather than booleans coming from the host)

I'm just thinking that synchronising the host and the FPGA might lead to problems so why bother.

[dotadk]

Hey BillTur,

Thanks for the reply. Unfortunately that will not work.

This app is a simulator, in which the cRIO is reading data using an analog input module from an outside source (a detector). The outside source will send continuous data, and an encoder will specify when the transmission of a new batch of data begins. The FPGA will handle the acquisition of the data, and will send it to the host. The host will then process each batch of data.

At this point I'm "simulating" the detector using the sending loop. After I solve this synch issue I will attempt to simulate the continuous behaviour.