Time violations in while loop

[Robot_obibok]

Hi

I want to ask about time violations in while loop. I thought that there is no time limits in while loop unless we use wait function, but I met time violations during compilation. I have solved the problem by using high throughput math library, but I still don't know from what depends time limits.

So I have a question.

What determine speed of while loop executing?

Is it frequency of analog output/ input or maybe something else?

Sorry if I have made some language mistakes,I'm not quite good in english.

[TFranjo]

Hi, 

Which error did you exactly get? 

Are you programming LV FPGA or LV RT?

Here is one KB explaining single-cycle timed loop:

http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD?OpenDocument

Regards

Franjo

[Robot_obibok]

Thanks for your interest.

I'm programming  LV FPGA.

Here is Timing Violation Analisys, you can see that my code need period longer then 24.75ns but I don't know what imposes that limit.

[Robbob]

There are many reasons this could occur.  The FPGA Clock is running at 40Mhz. 1/40,000,000 = 25ns, so it appears that the compiler is trying to run this loop at 1 tick yet is unsuccessful in routing that. Without more information on what the loop is trying to achieve, it is difficult to diagnose. Your multiply is taking a large amount of time, are you multiplying large arrays or something? Doing automatic data coercion(red dots on inputs)?

[Robot_obibok]

Here is my code(it is working now, eariel I was using normal multiply and add blocks instead of high throughput math). As you can see I'm using fixed-point type which needs large amount of time for every operation. I think it is possible that compilator is trying to run this loop at 1 tick, but when I added wait function within while-loop time violations still occured.

[TFranjo]

Hi,

I was checking bit more time violations inside while loop and I still do not understand what was happening! It seems that complier wanted to compile while loop as single cycle loop, but I do not know why. Can you please send me the vi which was making problems to you so I can test it on my computer. Which LV version do you use?

P.s.

Suggested way to use while loop timing on FPGA is by loop timer vi. Example is in the attachment. Here you can specify number of ticks!

Regards

Franjo

[TFranjo]

Here is the attachment 🙂

[Robot_obibok]

Here is project with time violations.Sorry that I didn't send it in one file but I can't use rar package as an attachment.

I'm using LV 2009 and PCI-7831R with Virtex 2.

[TFranjo]

Hi,

Somehow I have missed notification about post with your project, I realized it just now when I have checked service request.

I have tested code that you have sent and I do not get any time violations neither during compilation neither later with tool "Analyze Timing Violations".

I am using LV 2009!

As already discussed it should be normal behavior!

Regards

Franjo