Greetings!!
I am developing an applicaiton on the FPGA of the NI 5644R vector signal transceiver.
I have two single cycle timed loops: one 40MHz doing a convolution and writing to
a block memory FIFO, and the second one at 120MHz (sample clock) which reads from the
block memory FIFO and uses the values for subsequent interpolation...
Is it allowed to use a block memory-based FIFO to transfer values from a 40MHz loop
to a 120MHz loop (sample clock)??
The reason I am asking the question is that the compilation repeatedly fails reporting
the below error:
ERROR:HDLCompiler:69 - "/opt/apps/NIFPGA/jobs/J9k7Gwc_WXxzSVD/Interface.vhd" Line 193: <rioclk40outputwstreamwfifocountportfromreshold> is not declared.
Any inputs or suggestions will be helpful...
With best regards,
S. Kumar Raja
