Using Host memory buffers for data transfer between Host (RT) and target (FPGA)

[parsec43]

Apologies for the cross post. I realised this question is probably more suited to this forum.

I am a little confused by the usage of host memory buffers for host to target data transfer. When attempting to place host memory buffer methods on the FPGA, I get errors suggesting that I must use (all three) Write, Request and Retrieve data methods. 

Simplistically I would have assumed that I could just request and retrieve data methods on the FPGA, and use the Open host memory buffer VI on the RT to create an EDVR, and then use an in place element structure to write data from the RT host as the Host memory buffer white paper suggests.

https://www.ni.com/en/support/documentation/supplemental/17/host-memory-buffer-overview.html

Am I missing something here. Is there an example available that demonstrates a working FPGA and RT implementation of host memory buffers for fast data transfer from the host to target?

[benjamin-hinrichs]

Sorry for digging up this ancient topic, but information on this is scarce. Your suspicion seems to be correct.

There's a NI example (at least in LV2020) called "Additional FPGA Memory (Host Memory Buffer)" that uses all three methods, so I suspect this is the correct usage.