Using Host-to-Target FIFO to configure Block Memory for Linear Interpolation Table

[nanocyte]

Here's my understanding of what you're trying to do along with some optimizations I might try:

Also, FYI here's what a snippet is: http://www.ni.com/tutorial/9330/en/

[DanAllis]

Wow, goes to show how infrequently I've posted to the NI forum 🙂  Thanks for the instructions on the snippet capture.

I'm having a hard time understanding the design intent behind the optimization using the for loop within the FPGA while loop. Won't the FOR loop hold up the WHILE loop and limit the while loop execution speed? I guess it doesn't really matter since it is async anyway.

For the PID_UPDATE, I'm wondering if it would be better to update the complete PID param set at once to avoid instability from changing only one PID param at a time. With the custom memory type, the data is written and read as a complete param set.

Certainly good food for thought and I will give it more. Thank you for taking the time and helping!

[nanocyte]

The for loop only runs when you press the LUT_Update so most of the time it should be blazing fast. You bring up a good point though and the solution is to give each "update" it's own loop. That way, who cares if the while loop runs slow.

Yes, I was assuming you were updating the PID parameters before it saw any action. If you needed the data to be whole, you could put in your own arbitration. Keeping the control size small is a huge optimization and almost certainly worth it. If you did keep that mega control on the front panel, I don't see why you'd load it into block memory. You could just use that control directly instead.