Using all 8 slots in a cRIO

[soeren]

Hello

Im using a cRIO 9004 with a 1M  FPGA and 8 different I/O modules. I have been having some trouble using all of these modules at the same time in my FPGA vi. NI has a lot of examples on FPGA vi's with individual modules, but I'm having trouble fitting all 8 modules into the FPGA vi; it wont compile and says that to much space is used. What can I do? I have 8 modules, but cannot use all channels on them at once. How should my FPGA vi be built? with one while loop containing one FPGA I/O node with all channels?

Hope you can show me an example?

Søren

[xseadog]

Hi Søren,
welcome to the real world.
A 1M FPGA actually contains the equivalent of ~100K for an ASIC.
The actual max meory allocation is 80K. So do the maths, on a general average allocation that 10K. Not really a lot to work with.

Have you tried to ru n some of the examples that NI provide? Even though you have loaded you 8 slots does not mean that they have to be enabled!
So you should not have a major compiling  basic code examples.

Out of interest what 8 modules have you selected ?
If I was going to populate all 8 slots I would actually seriously consider the 3M FPGA.

Whta are you actually trying to achieve with your project?

Regards


xseadog

[soeren]

Hi

Thanks for the welcome ! I'm aware that the space is limited. The modules i'm using are AI 9205, AO 9263, 2 X Thermocouple 9211, DIO 9401, DO 9476, so its actually only 6 modules for now, and i'm by far not using all the channels on these modules. My FPGA vi doesn't contain any real code, no interrupts only while loop with a timed delay and the I/O node for a few channels for each of these modules. I removed my PWM block from the FPGA vi to make room for a few more AI channels.

To me it seems a bit strange having 8 slots and only using half of the channels on 6 modules. It's an expensive way of storing these modules

Any way my proceedure so was to copy and paste the different NI examples and then reduce them to a minimum to the FPGA vi.

[Morini]

Hi Søren,

I/O's(IO nodes) use alots of spaces compare with all other design stuff in LV FPGA. So you might want to reduce the I/O's first, if that is possible. Can you by the way tell me how many I/O's from each module were you using when compiling failed due to spaces issue on the FPGA?

There is an excellent example with NI-9205 module(NI Example Finder-> Hardware Input and Output-> CompactRIO->Module Specific->Analog Input->NI 9205 Advanced IO), that multiplexes the IO data FIFO instead of using the traditional I/O nodes for saving spaces on the FPGA. This example is special made for the 9205 module because the "large" numbers of the I/O's on the module(Only for NI 9205).

I presume you are using DMA's to transfer data from FPGA to RT. Using shared resources is not recommanded in LV FPGA.

Another option(the easy one) is to upgrade you backplane to a 3M gate version. With the 3M version you will have more room for testing and expanding your design. Please contact your local NI office for more infomation.

Best Regards!

[Christian_L]

Søren,

You may also want to consult some of the other resources on ni.com that address optmizing your LV FPGA code. Most likely there are things in your code (such as large front panel controls/arrays) that use up a lot of FPGA real estate.

Advanced FPGA Programming - Optimizing for Speed and Size

How Can I Optimize/Reduce FPGA Resource Usage?

[soeren]

Hi, thanks for the response.

I have started working with the implementation of some DMA FIFO from the FPGA, and would like to aquire the TC inputs from 3 9211 modules, and a few AI from 1 9201. Later on I would like to send out signals from a 9263 AO module and a few DIO from a 9401.

I expected the 9211 to be problematic in regards to keeping a high sampling rate, but I hoped that DMA could solve some of these issues. I started out with the "DMA buffered data aquisition" - example, but it seems like I'm not really getting very high sample rates from my 9211 loop on the FPGA, the minimum clock (Ticks) is around 20000000, which is only 2 Hz, and this is only with one module. I also tried to lower the sampling rate of the AO loop, but without any improvement. I'm using a cRIO 9012 with a 1M FPGA running LV 8.2.

What am I doing wrong, should the signal resolution be lowered to fit in more 9211's and increase the sample rate or are there other things that could be done.

Best regards soeren.

[Christian_L]

The sampling rate of the 9211 is expected to be low and what you see is normal. I.e. if you sample from all channels of one 9211 module it will take about half a second to receive back your readings. However, if you read channels from three 9211 modules in the same loop, all operations will be performed in parallel and the total acquisition time will not increase.

To acquire data from the 9211s and a 9201 at a higher rate, I suggest that you sample the 9211s in one loop and place their readings on a front panel indicator which will be used as a local variable. You could also use a global variable for this purpose which may save you some FPGA space.

In a separate loop sample the 9201 at the higher sample rate. In this loop also read the TC values from your local or global variable and build an array with all of your input values. Then pass this array to your DMA FIFO write. In effect you will be resampling the TC dat at a higher rate (repeating the same measurement value many times) and pass the resampled data to the DMA.

[mrak1]

Hi,

Another quick tip that may reduce the footprint on the FPGA ==> it is very simple to write multiple FPGA VIs and programmatically execute them on the cRIO.  This can be done even when the cRIO is already executing an application. 

Therefore, you may want to consider the following:

• Develop an FPGA VI to only read the calibration information from the 8 modules
• Develop a different FPGA VI to execute your application

From the host side you would do the following:

• On system startup ==> open and run the calibration FPGA VI to get the calibration coeff's off of the cRIO modules
• Close and abort this FPGA VI
• Open and run the main FPGA Application

I have been in a situation where the Calibration code on the FPGA VI has been nearly 1M by itself.  The only drawback is that your system will not support hot swapping modules without a reboot since the calibration coefficients will not be correct for the new module after switching.

I hope that this helps!

Mike