What is the "ideal" fifo size on FPGA Size

[weierand]

I am designing a FPGA application where I have to send data from the FPGA to the Host (PC).

- What is the maximum rate for a limited number of samples (n<100'000)

- What is the maximum rate for a unlimited number of samples (n<100'000)

- What is the advantage in these case to implement a fifo on the FPGA side that is bigger than 1 Elements (minimum is 15 Elements) when I can transfer the data directy to the ram and save space on the fpga (memory size on PC is much cheaper and bigger) 

Thanks

[Pixar]

Hi

So first what kind of hardware are you using for your project ?

The advantage of the FIFO is that you don´t have to do a polling. That means you can transfer very fast data from FPGA to the RT over the DMA.

And you can buffer your data, it is fast and a good solution to transfer big amounts of acquired data.

When you acquire only little amounts of data (one value or so), you can do it on the other way. You can write this value to a frontpanel

element on the host, but with this way you have to do a polling and the values woudn´t be buffered.

Real-Time VI to Host VI Communication Methods

http://digital.ni.com/public.nsf/allkb/48D244EC86971D3986256BD4005CCC28?OpenDocument

Real-Time FIFO for Deterministic Data Transfer Between VIs

http://zone.ni.com/devzone/cda/tut/p/id/3934

FPGAs - Under the Hood

http://zone.ni.com/devzone/cda/tut/p/id/6983

Kind regards

Beat

NI Germany

[weierand]

First of all thanks for your answer.

My FPGA is a 7831.

The Principe of DMA Transfer on NI-FPGA is in principle understood by me.

My question was more about the two different "method/ places" where I can allocate space for my DMA-Fifo.The One is on the PC side the other on the FPGA. But what is the advantage of allocating the DMA-Fifo on the FPGA at the place of allocating it directly on the PC Ram?

As example: a 20MHz Timed Loop send data (also @20 Mhz) through a DMA fifo of 15 Elements on the FPGA. On the Host side (PC) I allocated a Fifo size on the Ram of 100M Elements. With that Configuration I had no Problem to read all data continiously (Over some seconds).

What will be the advantage of allocating more space on the PGA side????

Best regards

Andreas Weier

Message Edited by weierand on 12-04-2009 02:43 AM

[Pixar]

Hi Andreas

First point, it is not possible to use a data acquisition with an FPGA without allocating RAM on the FPGA.

The advantage to allocate more  space on the FPGA side is that you can transfer faster or when you have bigger amount of data.

You have multiple possiblities to create a FIFO or space on the FPGA: RAM, LUT and FlipFlop

LUT and FipFlop you can only use with the option target scoped, that means also single processed.

So that you can´t use to transfer data to the host.

When you like to transfer data to host, you have to use FPGA RAM and then with the FIFO you can send the data from the FPGA to the host.

But the FPGA RAM is even faster then your host RAM, but you allways need both of them.

With a bigger FPGA space you can transfer more data within a smaller space of time.

Hope that helps?

Kind regards

Beat

NI Germany