Whats the maximum data rate possible between RT controller and FPGA

[Mr._Ash]

Hi
I'm using crio-9014, 400MHz Real Time controller with 8 modules, and i'm using a crio 9104 8 slot chassis.
I want to know whats the maximum data rate/ bandwidth in bits/ second possible between RT controller and FPGA.
Please reply at the earliest

[The Specialist]

Hi AnishG,

I think that that question is very difficult to answer.  I think the reason is because it involves determining how you want to push the limits of the FPGA and real-time controller, and what tradeoffs that will have.  You could send point-by-point from the FPGA to the RT side by using interupts.  Or you could load data up in a DMA FIFO and send it in chunks.  The later is faster, but in a controls application sometimes you need data to get to the RT faster which would call for smaller chunks.  All of which is a load balancer  problem.  Plus the larger the chunk of data you send, the more FPGA you use up.  And the more channels you collect data from the more FPGA you use up.  Most cases you need to find what your limiting factor is.

Sorry that wasn't a perfect answer, but since FPGA can be programed to what you want it to be, the answers have many factors.  On another note I would assume that rate of acquisition would be similar to that of cDAQ which can use similar modules.

[Mr._Ash]

Hi
Thanks alot for the reply....... I got the information from NI itself. With FIFO we can transfer 4.3MB data( theoretical). I'm going to try that.
Thanks and regards
AnishG

[WillD]

I am not sure what number that is, but it is not close at all to a theoretical maximum.

Using just the default clocks the FPGA can write just over 152MB/s, 32 bits * 40MHz, for one DMA channel; there are 3 available.

The fastest I was able to clock a DMA write on the FPGA, cRIO-9102, was 98.46 MHz, or just over 375MB/s for one channel.

While the fastest DMA read was clocked at 125MHz or 476 MB/s for one channel.

[Bassett_Hound]

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WillD wrote:

I am not sure what number that is, but it is not close at all to a theoretical maximum.

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I think this number came from the actual data throughput (8 Modules, 4 Channels at 24bits/sample all at 50KS/sec ~ 4.8MB/sec ), although the number 4.3 MB/sec seems to be a little low compared to my math.  However, the theoratical maximum for throughput from an FPGA device is in general much higher than the controller can consume, especially with cRIO controllers.  This is because the DMA channel from a cRIO backplane is the only device on the PCI bus and has full access to the PCI bandwith.  In this situation, its really the cRIO controller thats drinking from the fire hose and is the limiting factor on the amount of data that can be transfered.  If your not doing anything with the data, I've seen upwards in the range of 50 MB/sec.  However, doing nothing with the data is not really usefull for an applicaiton other than benchmarking the maximum amount of throughput you can get from the cRIO backplane to the controller.

For typical applications, its really the processing that your wanting to do on the data thats going to limit the amount of data you can transfer from the FPGA, and at least for cRIO, you don't really need to know the theoretical maximum of the DMA throughput from the FPGA to the RT controller.  For example, if your logging to disk, a typical app might get around ~1.5 MB/sec write speed, which means if your trying to acquire and log continuously, then the logging to disk is the limiting factor.  You could also have an application thats performing an FFT or some other intentive math calulation that is limiting the amount of data you can process, which is probably why the Specialist said its a hard question to answer.

Of course, this is all with regards to using a cRIO controller and backplane.  If your using a PXI with R-series boards, you now share the PCI bandwidth with other devices so you have and need to take that into account.  In general though, the RT controllers are going to be more powerful, hence more processing speed which is nice if you need the speed.

Hope that helps,

Basset Hound

Message Edited by Bassett Hound on 05-15-2008 10:47 AM

[WillD]

I understand the effect of crunching numbers, the values I gave were for straight reads and writes for maximum bandwidth possible, in a burst situation.

As far as modules, going with 9205s you should be able to aquire up to 122MB/s, 2 bytes x 32 channel x 8 modules at 250kS/s.