Xilinx Compilation Error

[BillTür]

Hello,

I am having troubles compiling some FPGA code. I was able to compile similar VIs but not this one. There have been several changes in the code.
The following error pops up:

Compilation failed due to a Xilinx error.

Details:
ERROR:sim - Input_Depth: Invalid value '16777216'.
ERROR:sim - Failed to initialize fifo_generator_v5_3 IP model.
   Input_Depth: Invalid value '16777216'.
ERROR:sim - Unable to configure IP model for generator
   'implementation_netlist_generator'.
ERROR:sim - Failed to generate 'builtinfifocorefpgawfifon9'.
   Unable to configure IP model for generator
   'implementation_netlist_generator'.
ERROR:sim:554 - Error found during execution of IP builtinfifocorefpgawfifon9
   (Fifo Generator version 5.3)

I tried copying the VI into a blank one like suggested here: http://forums.ni.com/t5/LabVIEW/fpga-ERROR-sim-Input-Depth-Invalid-value-xxxx/td-p/1903379

Which worked for some other VIs first but has no effect anymore.

I checked this article but I don't think it applies to my LV version: http://digital.ni.com/public.nsf/allkb/BBD7A87F2ADC2028862577FB005F6B19

Compilation settings:

Compiling on local compile server
Compilation Tool: Xilinx 12.4

It is supposed to be compiled for a FlexRIO 7965R in a PXIe Chassis. I am running Labview 2011.

I have attached the Xilinx log.

Please do question me if the problem is not clear.

Any help is much appreciated.

Thank you!

[PeterFoerster]

Hi,

Please correct me, if I understood you incorrectly:

You can- right now- compile another application, so we can rule out an error with the application itself.

Your application, which you adapted from the application that compiled fine, doesn't compile and gives back the message you posted.

I think the next lgical step is to find out at what point in the development from the initial application to the current one the compiler starts failing. Maybe you could delete parts of the new code (always back up what you have) and try compiling several times.

From the Errors you posed in your initial post, I'd look for any IP that was integrated into the Program.

Please check back to report any progress or lack of thereof

best regards,

[BillTür]

Hello,

Thanks for replying!

Exactly, yes. The other issue is that I don't want to compile the code too often because it is very time-consuming (1 - 1.5 hrs). The code has become quite complex..
Today, I got a new version of the code to compile again (not with parts deleted but a - say - new version of the VI).

I'm only using LabView primitives I think.

Right now I am not investigating this further because I'm lacking the time but it is a quite annoying problem and it might pop up again.

[BillTür]

With LabView primitives being not entirely correct. I'm also using FIFOs and block memory.

Sorry for double post.

[Hitesh_Dhola]

Dear Peter,

I am also facing same problem and same error.. I know exactly when did this error came.. I inserted two target scoped FIFO to write into and this error started before that , I was using local variable to transfer data. No error.

I am using DMA FIFO for seperate function from the beggining but no error uptill I introduced "two target scoped FIFO"

Hitesh Dhola

Control system Engineer, ITER-India

[Hitesh_Dhola]

Oh... Removed Block Memory from Project (Was just created but not used in VI)... Reduced size of FIFO from 1024 to 512.. and good to go.. succesfully compiled.. Lets see how it works.. :)

Regards,

Hitesh Dhola

Control system Engineer, ITER-India

[BillTür]

If you should have problems with this in the future, try switching implementation from "Target Optimal" to something else. I'm afraid I can't find where I found this information.

Regards,

Bill

[Hitesh_Dhola]

Damn.. It failed when I re-compiled witout changing any thing... 

I again changed control logic implementation from "Optimal" to "Built-In" and it compiled successfully. I am not now sure that re-compilation will work or not..

Hope it works..

Hitesh Dhola

Control System Engineer, ITER-India