Bitgen fails the DRC with the following error. I can post my VI/VHDL code if it is of any help.
ERROR:PhysDesignRules:1061 - Dangling pins on
block:<window/theVI/n_910/MiteInterfacex/DmaBlk.DmaComponents[0].GenUsedDmaCh
annel.MiteDmaComponentx/Input.DmaInputx/MiteReadInterfacex/inst_Mram_mem/wind
ow/theVI/n_910/MiteInterfacex/DmaBlk.DmaComponents[0].GenUsedDmaChannel.MiteD
maComponentx/Input.DmaInputx/MiteReadInterfacex/inst_Mram_mem.A>:<RAMB16_RAMB
16A>. The block is configured to use DIPA[0-1] but some of those pins are
not connected.
WEA of comp
window/theVI/n_910/MiteInterfacex/DmaBlk.DmaComponents[0].GenUsedDmaChannel.M
iteDmaComponentx/Input.DmaInputx/MiteReadInterfacex/inst_Mram_mem/window/theV
I/n_910/MiteInterfacex/DmaBlk.DmaComponents[0].GenUsedDmaChannel.MiteDmaCompo
nentx/Input.DmaInputx/MiteReadInterfacex/inst_Mram_mem.A has an active signal
but no data input pins are connected. Invalid data may be written to the
BlockRAM.
