In the LabVIEW examples for a NI9239 and stated in the cRIO developer guide, NI indicates that the loop rate for a delta sigma module can be controlled by the sample rate settings in the modules properties instead of having to use a loop timer. I tried to prove this and put a tick count in the loop with the I/O node. In the modules properties, I set the sample rate to 5kS/s. I should be seeing 8000 ticks. I ran this on a cRIO 9035 (sync) and observed that the tick count was 8000 most of the time, but there were periodic (about every 6ms) drops to 7999 ticks.
Is this because of the DSM has its own clock and is not synchronized to the FPGA 40MHz clock? If so, how can I verify that the time between samples is exact? Would there be any detrimental effects if I just dropped a loop timer inside set for 8000 ticks? Additionally, is it acceptable to use a loop timer set for a slower sampling rate than what the rate in the module properties is set to?
