cRIO Scan Engine; Missing points in RT

[Jed_Davidow]

How many years have I been using these FIFOs and never read the manual?  Dude.  Thank you for the Blocking/Polling info.  Has that always been available?  I took the FPGA course when the RIO was first intorduced with LV7.  They didn't mention it and I never noticed those options in any examples I have come across.  (Is there a similar situation for VISA reads?!)

As for the missing data...

I did verify the timer on the timed loop.  As I increase the speed of the Scan Engine, the timed loop TimeStamp becomes more erratic.  If the loop time is supposed to be 2000us, when things get erratic (but still no data loss) I see complimentary loop times... 1.3/.7, 1.6/.4; so the loop is recovering.  Once it gets too fast, you see spikes in the loop time, but no complimentary lower time following it- so the TimedLoop missed the scan.  If it's set way too fast, we essentially see loop times 2x what they should be, as it misses every other point.

What I was concerned about was WHY this was happening- the Timed Loop was set to be synchronous at 4000us- something the RT should be able to handle without issue.  If fact, there was no problem with the timed loop if I set it to have its own 4000us loop time, non-syched to the ScanEngine.  This leads me to believe that the problem with the transfer was originating with something on the Scan Engine.

Indeed, after reformatting the memory, the problem seems to be solved.  So either 1) Something was messed up with the factory-installed image that I erased that affected the Scan Engine or 2) due to my swapping hardware (assuming the bitfile for the Scan Engine was the same for all FPGAs) the SCan Engine was running in some gimpy state.

I suspect #2, but I won't rule out #1 just yet (I have access to a second 9076 that's still got a factory flash image and is having this trouble).  I'll try to load the code that's running perfectly on the first 9076 and the other 9076 and see if it works.  If not, I'll flash and reload and see if that fixes it.  I'll report the info.

Just a quick question- does anyone know if I need to/there is a way to force the Scan Engine bitfile to be updated on the target?  Apart from reflashing the memory?

[StephenB]

The RT FIFO read write mode options are new since LabVIEW 8.2

Yes, VISA has the same options. They are called slightly different things, but the effect is about the same. It is called "Synchronous" or "Asynchronous" mode. See the detailed help on the read and write. Synchronous is basically polling (100% cpu use) and Asynchronous is basically blocking (0% cpu use). You change modes by right clicking the node, and the default on cRIO and Windows is Asynchronous.

So we know that the data isn't being read in the first place, so it's a timed loop/scan engine problem. Note, you can get more detailed information about the timed loop iteration by looking at the left data node. There are things in there under "previous iteration timing" like "finished late?" or "iteration duration" that might be helpful.

I can't explain why you would ever be missing points like that. The behavior is very strange. If you could ever reproduce it easily, I recommend calling ni directly and even volunteer to send in hardware/software if the support engineer can't reproduce it.

I think you can force the scan engine to be redeployed by right clicking the chassis and going to undeploy then deploy. Not sure though.