compiling an fpga vi

[margarette]

Hi. I'm trying to compile a certain simple FPGA VI (with no errors). However, everytime I compile my code, LabVIEW eventually stops responding. I'm using a PXIe - 7962R module (NI FlexRIO). What can I do to solve this problem? Thank you for your time.

[Larry_H]

Margarette,

I have a couple preliminary questions for you:

1. What version of LabVIEW are you using?

2. What version of the Xilinx Compile Tools are you using?

3. What version of the NI-RIO driver do you have installed?

4. When you say that LabVIEW eventually stops responding, are you getting a timeout error? Is it freezing up? 

5. Is this the first time that this has happened?

6. Were you ever able to compile with your setup?

Can you provide any screenshots to show where you're running into this issue?

[margarette]

Hello! Thank you for replying. Here are my answers to your questions:

1. I'm using LabVIEW 2011

2. NI LabVIEW FPGA Xilinx 12.4 Tools

3. NI RIO 4.0

4. the compilation freezes up at a certain point and then a crash reporter appears . Attached is the screen shot where the compilation always stops.

5. I have successfully compiled some sample FPGA VIs and some of my own FPGA VIs as well.

I hope you can help me. Thank you so much. 🙂

[margarette]

Hi, attached in the previous message is the crash reporter. Here is another screen shot where the compilation stops...

[Larry_H]

Margarette,

From your description, would I be correct in my assumption that you have no problems compiling other VIs but it is this specific VI that you cannot compile? If so, would you mind attaching your project to your post so I could possibly look at it and try compiling on my computer also? I'd like to see if I could replicate what you're seeing and maybe determine why it's failing. If this isn't possible, could you perhaps upload a screenshot of your block diagram, front panel, and project explorer window?

Regards,

Larry H.

[Larry_H]

Margerette,

Are you using a sine wave generator VI in your project? If so, that may explain why your code is hanging during compilation. To avoid this issue stop the process "ssoShell.exe" which will stop 4 other Passlogix processes with it, then try to compile again.

Regards,

Larry H.

[margarette]

Hello sir Larry! I just edited the sample flexRIO project "Generate Sine Wave.lvproj" and used this as the project where I put and compile my codes (some of my codes were easily compiled under this project). I tried deleting the generate sine wave VIs, and also, I tried using a new project but the code is still hanging during compilation. There is also no ssoShell.exe process in the the Windows Task Manager while I'm compiling.

So far, this is the only FPGA VI that I cannot compile. I will attach my project together with the subVIs. I checked the two subVIs and they are perfectly running as FPGA VI. But the top-level VI is the one that encounters problems in compiling. My codes are very simple. They just deal with concatenation of arrays. 

Out of curiosity I tried to drastically reduce the sizes of the arrays and the code finally compiled.  I have a feeling that the array sizes are the reason for the problem in compiling. My desired total number of elements is 7160. Each element is just one bit. Are there ways to make my VIs more efficient without reducing the size of my arrays? I tried using a single-cycle timed loop but the compilation still hangs.

Sir, thank you so much for your time. I really appreciate it. 🙂

[Larry_H]

Margarette,

Is the project you attached all that you're trying to compile in the project? I downloaded your project and tried compiling it and I was able to compile successfully and the estimated disk usage was only 13.7%. Or did you, perhaps provide me with a modified version of your project?

Additionally, I wanted to provide you with some literature, to read at your leisure, that discusses using large arrays in regards to FPGA projects: Why Shouldn't I use Large Arrays When Developing FPGA Applications? and Using Clusters and Arrays in LabVIEW FPGA

In regards to your current arrays, I know you mentioned that each element is a single bit. Do you intend to read/write an individual bit one at a time, or do you intend to access groups of bits? I ask because there's also the option of using U32 or U8 to access multiple bits at once instead of doing them on a bit by bit basis.

Regards,

Larry H.

[margarette]

Hello sir! The project I attached is exactly the same project that I use in compiling my VI, but it is still not compiling. What could be the possible reason that the code is compiling in your computer and not in my computer? Thank you.

[margarette]

Hello sir, I removed the array indicator in my code since I read that front panel arrays use more FPGA gates and therefore reduces code efficiency. The VI now looks like the first attached picture.This code finally compiled successfully. Now, my problem is how can I transfer this data to the host VI since the code does not compile when I use an array indicator. Also, I tried using FIFO. The code with FIFO has no error but it still didn't compile. My code with FIFO looks like the second attached picture. Thank you.