04-03-2006 01:50 PM
04-05-2006 08:25 AM
Hi areochem,
To answer the first question the insane message you get is a known issue with LabVIEW FPGA 8.0 and the block diagram grid alignment option. It will typically happen after placing the VI on the diagram and selected a FPGA VI for the reference that has a bitfile compiled. When enabled, the grid alignment causes the scripted LabVIEW code generated by the FPGA Open VI Reference.vi to throw insane object errors.
Workaround: Turn off the diagram grid alignment option:
Tools » Options » Alignment Grid » Enable diagram grid alignment (uncheck)
For the second question you should be able to use a Loop Timer in a while loop with a IRQ. There is an example ( Interrupt Method for synchronization ) shipped out with with the FPGA module that does this exact setup. Its possible your host may not be acknowledging the IRQ fast enough causing the delay. Another option you might have is to make use of DMA transfers back to the host. You might also check out the following link.
What is the Best Method For Synchronizing a LabVIEW FPGA and a Host Interface VI?
http://digital.ni.com/public.nsf/websearch/5930DB001A07F988862570BB001DF031?OpenDocument
Hope this helps,