fpga i/o node with a certain frequency

[scorer]

hi

I'm trying to sample 4 analog channels at 65536 Hz and pass the data through a DMA FIFO to my host VI. Using the normal clock speed of 40 MHz the closest I can get to this sampling frequency is 65574 Hz. Is there a way to get closer to my desired sampling frequency?

Maybe there is a way to do it with derived clock frequencies e.g. 85Mhz and executing the sampling only every 1297th iteration but I haven't found a way to implement that yet.

Thank you in advance

[scorer]

my software details are:

Labview FPGA  version 8.6 

NI Hardware : RIO (cRIO, R Series, FexRIO, sbRIO) device PCI-7833R Driver version: 3.0.1

Operation system: Windows XP

[WillD]

Seems you have it pretty much figured out.

You can either:

1. Make the derived clock and set it as the New FPGA base clock.  (You may have trouble meeting timing elsewhere with the faster clock.)

   a. Make a while loop with a wait timer placed inside

   b. set the timer to ticks and have it wait 1297 ticks.

2. Make your own wait timer

  a. Make a SCTL and clock it at your derived 85MHz.

  b. Make a counter through shift registers on the SCTL.

  c. Compare the counter to 1297 and stop the SCTL when equal.

    (The only trouble here is entering and leaving loops will take some ticks, you will have to adjust the 1297 down depending how you code the loop around your new timer.

Message Edited by WillD on 10-22-2009 08:53 AM

[scorer]

Changing the FPGA Base clock doesn't work, because the target only supports top-level clocks of 40M, 80M....200M.

I also have tried the second possibility, but the code around the new timer is a little bit complex and i haven't found the right counter yet.

But if there isn't another way to get the frequency, I will spend some time and take this way.

[WillD]

You could do something like that is attached.  I did not use a flat sequence figuring the Analog sampling would occur while the timer runs so the samples should be closer to your 65536Hz apart.  The 1297 will still probably need to be adjusted.

You may be able to play with the conversion rate on the Analog card itself, using it to time the loop.  I do not know how accurate that timing is though, it just claims Minimum time between conversions.

Edit: The conversion timing is locked at multiples of the 25ns tick frequency unfortunately.

Message Edited by WillD on 10-22-2009 10:36 AM

Message Edited by WillD on 10-22-2009 10:36 AM

[scorer]

Thanks for the VI

It seems that i can work with this method and can get a little bit closer to my 65536 Hz.