05-29-2006 11:55 AM
05-29-2006 07:30 PM
try these
05-30-2006 01:12 AM
05-30-2006 08:05 AM
Here is an architecture overview:
http://zone.ni.com/devzone/conceptd.nsf/webmain/925A7C29B99BE5C286256EE40079F0B8
The FPGA backplane (where the modules are) connects to the RT controller via a PCI bus. There are interrupt, polling, and DMA schemas for data transfers, signaling and related communications between the FPGA LabVIEW code and the RT LabVIEW code.