look-up table with variable entries ?

[Laurent80]

Hello,

I want to write a FPGA application that generates (through analog output) some non-linear profile depending on the value of an analog input. The profile I want to ouput is defined through 512 values.

My problem is that I need to be able to define my profile (so the 512 16-bits integers) remotly from the host-VI (not periodically, but via some init-mode). No chance with an fixed-size 1D array of 512 integers (I confess: I tried it 🐵 , so I thought about a look-up table. But I didn't find some way to initialize that table remotly (I understood from the FPGA module user manual it should be possible somehow :"...For larger look-up table, use the Look-up Table 1D VI available with the FPGA Module to create look-up tables with variable entries in the FPGA memory..."). Is it possible at all ?

Or should I maybe use FIFO or memory items ? (I don't have experience with these 2 functions yet)

Thank you in advance for the help,

Laurent

[Spectre_Dave]

Laurent

You should be able to create a VI Scoped Memory for the FPGA.  http://zone.ni.com/reference/en-XX/help/371599B-01/lvfpga/fpga_vi_scoped_memory/#details.  You can then Write (initialize) and Read the memory.  You can DMA the lookup data from the host to the FPGA Target where you can fill the VI scoped memory.

[Christian_L]

Similar to VADave's reply, you can also use a target-scoped memory block. This would allow you to write to the memory block in one (sub)VI of your FPGA application and read from it in another (sub)VI. The VI-scoped memory block, as the name implies, can only be written to and read from in the same VI.

The benefit of a VI-scoped memory block is that you can create one reentrant subVI with such a memory block and then create several instances of the subVI in your main VI, each with their own instance of the memory block.

[Laurent80]

Thank you to both of you!

Now I'm trying to implement your solution (DMA and memory block). But I'm not familiar with the using of the DMA FIFO, and I don't manage to synchronize the host-VI (writing of the array in the FIFO) and the FPGA-VI (reading the elements of the array one-by-one from the FIFO to write them in the memory) properly. The LabVIEW Help confused me a little bit on that... could you maybe give me some tip, or show me a small example similar to what I want to do ?

Thank you in advance,

Laurent

[Christian_L]

Here's one possible implementation. I didn't add much code for synchronization but if the host VI forces the FPGA to reset and restart the FPGA VI, then we know the FPGA code is waiting for the 512 data points from the DMA buffer before doing anything else.

You need to define the DMA FIFO (DMA Out in my example) and FPGA memory block (MyLUT in my example) in the project.

Note that DMA from host to FPGA does not work on the cRIO-9002 and cRIO-9004 controllers.

Host Code

FPGA Code

Message Edited by Christian L on 11-21-2007 11:44 AM

[Laurent80]

Thank you very much Christian, you really helped me !

Laurent